Firmware/opensbi
8
0
Fork 0
forked from Mirrors/opensbi
Code Pull Requests Activity

include: Extend get_insn() to read instruction from VS/VU mode

Browse Source 
Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.

This patch extends get_insn() to read instruction from VS/VU mode.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
2019-08-17 20:54:40 +05:30
committed by Anup Patel
parent a14e7ee82c
commit 7d4420bd69
4 changed files with 47 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
lib/sbi/riscv_unpriv.c
View File

@@ -97,20 +97,22 @@ void store_u64(u64 *addr, u64 val,
}
#endif
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
struct unpriv_trap *trap)
{
ulong __mstatus = 0, val = 0;
ulong __mstatus = 0, __vsstatus = 0, val = 0;
#ifdef __riscv_compressed
ulong rvc_mask = 3, tmp;
#endif
if (trap) {
trap->ilen = 4;
trap->cause = 0;
trap->tval = 0;
sbi_hart_set_trap_info(scratch, trap);
}
trap->ilen = 4;
trap->cause = 0;
trap->tval = 0;
sbi_hart_set_trap_info(scratch, trap);
if (virt)
__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
#ifndef __riscv_compressed
asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
#if __riscv_xlen == 64
@@ -134,21 +136,23 @@ ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc),
[rvc_mask] "r"(rvc_mask));
#endif
if (trap) {
sbi_hart_set_trap_info(scratch, NULL);
switch (trap->cause) {
case CAUSE_LOAD_ACCESS:
trap->cause = CAUSE_FETCH_ACCESS;
trap->tval = mepc;
break;
case CAUSE_LOAD_PAGE_FAULT:
trap->cause = CAUSE_FETCH_PAGE_FAULT;
trap->tval = mepc;
break;
default:
break;
};
}
if (virt)
csr_write(CSR_VSSTATUS, __vsstatus);
sbi_hart_set_trap_info(scratch, NULL);
switch (trap->cause) {
case CAUSE_LOAD_ACCESS:
trap->cause = CAUSE_FETCH_ACCESS;
trap->tval = mepc;
break;
case CAUSE_LOAD_PAGE_FAULT:
trap->cause = CAUSE_FETCH_PAGE_FAULT;
trap->tval = mepc;
break;
default:
break;
};
return val;
}