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platform: andes/ae350: Implement hart hotplug using HSM extension

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Add hart_start() and hart_stop() callbacks for the multi-core ae350
platform, it utilizes the ATCSMU to put the harts into power-gated
deep sleep mode. The programming sequence is stated as below:

1. Set the wakeup events to PCSm_WE
2. Set the sleep command to PCSm_CTL
3. Set the reset vector to HARTm_RESET_VECTOR_{LO|HI}
4. Write back and invalidate D-cache by executing the CCTL command L1D_WBINVAL_ALL
5. Disable I/D-cache by clearing mcache_ctl.{I|D}C_EN
6. Disable D-cache coherency by clearing mcache_ctl_.DC_COHEN
7. Wait for mcache_ctl.DC_COHSTA to be cleared to ensure the previous step is completed
8. Execute WFI

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yu Chien Peter Lin
2023-01-20 11:05:11 +08:00
committed by Anup Patel
parent 9c4eb3521e
commit 787296ae92
4 changed files with 180 additions and 1 deletions
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70
platform/generic/andes/sleep.S Normal file
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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2023 Andes Technology Corporation
*
* Authors:
* Yu Chien Peter Lin <peterlin@andestech.com>
*/
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_asm.h>
#include <andes/andes45.h>
.section .text, "ax", %progbits
.align 3
.global __ae350_disable_coherency
__ae350_disable_coherency:
/* flush d-cache */
csrw CSR_MCCTLCOMMAND, 0x6
/* disable i/d-cache */
csrc CSR_MCACHE_CTL, 0x3
/* disable d-cache coherency */
lui t1, 0x80
csrc CSR_MCACHE_CTL, t1
/*
* wait for mcache_ctl.DC_COHSTA to be cleared,
* the bit is hard-wired 0 on platforms w/o CM
* (Coherence Manager)
*/
check_cm_disabled:
csrr t1, CSR_MCACHE_CTL
srli t1, t1, 20
andi t1, t1, 0x1
bnez t1, check_cm_disabled
ret
.section .text, "ax", %progbits
.align 3
.global __ae350_enable_coherency
__ae350_enable_coherency:
/* enable d-cache coherency */
lui t1, 0x80
csrs CSR_MCACHE_CTL, t1
/*
* mcache_ctl.DC_COHEN is hard-wired 0 on platforms
* w/o CM support
*/
csrr t1, CSR_MCACHE_CTL
srli t1, t1, 19
andi t1, t1, 0x1
beqz t1, enable_L1_cache
/* wait for mcache_ctl.DC_COHSTA to be set */
check_cm_enabled:
csrr t1, CSR_MCACHE_CTL
srli t1, t1, 20
andi t1, t1, 0x1
beqz t1, check_cm_enabled
enable_L1_cache:
/* enable i/d-cache */
csrs CSR_MCACHE_CTL, 0x3
ret
.section .text, "ax", %progbits
.align 3
.global __ae350_enable_coherency_warmboot
__ae350_enable_coherency_warmboot:
call ra, __ae350_enable_coherency
j _start_warm