forked from Mirrors/opensbi
platform: andes/ae350: Implement hart hotplug using HSM extension
Add hart_start() and hart_stop() callbacks for the multi-core ae350 platform, it utilizes the ATCSMU to put the harts into power-gated deep sleep mode. The programming sequence is stated as below: 1. Set the wakeup events to PCSm_WE 2. Set the sleep command to PCSm_CTL 3. Set the reset vector to HARTm_RESET_VECTOR_{LO|HI} 4. Write back and invalidate D-cache by executing the CCTL command L1D_WBINVAL_ALL 5. Disable I/D-cache by clearing mcache_ctl.{I|D}C_EN 6. Disable D-cache coherency by clearing mcache_ctl_.DC_COHEN 7. Wait for mcache_ctl.DC_COHSTA to be cleared to ensure the previous step is completed 8. Execute WFI Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:

committed by
Anup Patel

parent
9c4eb3521e
commit
787296ae92
@@ -10,6 +10,104 @@
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#include <platform_override.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/sys/atcsmu.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_init.h>
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#include <andes/andes45.h>
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static struct smu_data smu = { 0 };
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extern void __ae350_enable_coherency_warmboot(void);
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extern void __ae350_disable_coherency(void);
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static __always_inline bool is_andes25(void)
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{
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ulong marchid = csr_read(CSR_MARCHID);
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return !!(EXTRACT_FIELD(marchid, CSR_MARCHID_MICROID) == 0xa25);
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}
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static int ae350_hart_start(u32 hartid, ulong saddr)
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{
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/* Don't send wakeup command at boot-time */
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if (!sbi_init_count(hartid) || (is_andes25() && hartid == 0))
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return sbi_ipi_raw_send(hartid);
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/* Write wakeup command to the sleep hart */
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smu_set_command(&smu, WAKEUP_CMD, hartid);
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return 0;
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}
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static int ae350_hart_stop(void)
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{
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int rc;
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u32 hartid = current_hartid();
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/**
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* For Andes AX25MP, the hart0 shares power domain with
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* L2-cache, instead of turning it off, it should fall
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* through and jump to warmboot_addr.
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*/
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if (is_andes25() && hartid == 0)
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return SBI_ENOTSUPP;
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if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
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return SBI_ENOTSUPP;
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/**
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* disable all events, the current hart will be
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* woken up from reset vector when other hart
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* writes its PCS (power control slot) control
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* register
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*/
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smu_set_wakeup_events(&smu, 0x0, hartid);
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smu_set_command(&smu, DEEP_SLEEP_CMD, hartid);
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rc = smu_set_reset_vector(&smu, (ulong)__ae350_enable_coherency_warmboot,
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hartid);
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if (rc)
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goto fail;
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__ae350_disable_coherency();
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wfi();
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fail:
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/* It should never reach here */
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sbi_hart_hang();
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return 0;
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}
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static const struct sbi_hsm_device andes_smu = {
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.name = "andes_smu",
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.hart_start = ae350_hart_start,
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.hart_stop = ae350_hart_stop,
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};
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static void ae350_hsm_device_init(void)
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{
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int rc;
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void *fdt;
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fdt = fdt_get_address();
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rc = fdt_parse_compat_addr(fdt, (uint64_t *)&smu.addr,
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"andestech,atcsmu");
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if (!rc) {
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sbi_hsm_set_device(&andes_smu);
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}
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}
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static int ae350_final_init(bool cold_boot, const struct fdt_match *match)
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{
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if (cold_boot)
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ae350_hsm_device_init();
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return 0;
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}
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static const struct fdt_match andes_ae350_match[] = {
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{ .compatible = "andestech,ae350" },
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@@ -18,4 +116,5 @@ static const struct fdt_match andes_ae350_match[] = {
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const struct platform_override andes_ae350 = {
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.match_table = andes_ae350_match,
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.final_init = ae350_final_init,
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};
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