forked from Mirrors/opensbi
lib: sbi: use 64 bit csr macros
Switch the most obvious cases to new macros. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-4-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
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@@ -86,10 +86,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
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}
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMSTATEEN)) {
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mstateen_val = csr_read(CSR_MSTATEEN0);
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#if __riscv_xlen == 32
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mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
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#endif
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mstateen_val = csr_read64(CSR_MSTATEEN0);
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mstateen_val |= SMSTATEEN_STATEN;
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mstateen_val |= SMSTATEEN0_CONTEXT;
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mstateen_val |= SMSTATEEN0_HSENVCFG;
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@@ -110,17 +107,11 @@ static void mstatus_init(struct sbi_scratch *scratch)
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else
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mstateen_val &= ~SMSTATEEN0_CTR;
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csr_write(CSR_MSTATEEN0, mstateen_val);
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#if __riscv_xlen == 32
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csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
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#endif
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csr_write64(CSR_MSTATEEN0, mstateen_val);
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}
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if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) {
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menvcfg_val = csr_read(CSR_MENVCFG);
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#if __riscv_xlen == 32
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menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
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#endif
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menvcfg_val = csr_read64(CSR_MENVCFG);
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/* Disable double trap by default */
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menvcfg_val &= ~ENVCFG_DTE;
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@@ -156,10 +147,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SVADE))
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menvcfg_val &= ~ENVCFG_ADUE;
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csr_write(CSR_MENVCFG, menvcfg_val);
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#if __riscv_xlen == 32
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csr_write(CSR_MENVCFGH, menvcfg_val >> 32);
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#endif
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csr_write64(CSR_MENVCFG, menvcfg_val);
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/* Enable S-mode access to seed CSR */
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZKR)) {
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@@ -139,12 +139,7 @@ void sbi_timer_event_start(u64 next_event)
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* the older software to leverage sstc extension on newer hardware.
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*/
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if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSTC)) {
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#if __riscv_xlen == 32
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csr_write(CSR_STIMECMP, next_event & 0xFFFFFFFF);
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csr_write(CSR_STIMECMPH, next_event >> 32);
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#else
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csr_write(CSR_STIMECMP, next_event);
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#endif
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csr_write64(CSR_STIMECMP, next_event);
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} else if (timer_dev && timer_dev->timer_event_start) {
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timer_dev->timer_event_start(next_event);
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csr_clear(CSR_MIP, MIP_STIP);
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