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lib: Rename unprivileged trap handler

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Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.

Rename it to "expected" trap handler as it will be used in other cases in
future.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Atish Patra
2020-05-09 16:47:23 -07:00
committed by Anup Patel
parent 7be75f519f
commit 63a513edec
5 changed files with 17 additions and 17 deletions
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6
lib/sbi/sbi_unpriv.c
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@@ -21,7 +21,7 @@
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
type ret = 0; \
trap->cause = 0; \
asm volatile( \
@@ -51,7 +51,7 @@
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
trap->cause = 0; \
asm volatile( \
"add %[tinfo], %[taddr], zero\n" \
@@ -120,7 +120,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
register ulong tinfo asm("a3");
register ulong ttmp asm("a4");
register ulong mstatus asm("a5");
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr();
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr();
ulong insn = 0;
trap->cause = 0;