forked from Mirrors/opensbi
platform: Move ariane standalone fpga project to its own project
Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Atish Patra
36
platform/fpga/ariane/config.mk
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36
platform/fpga/ariane/config.mk
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (C) 2019 FORTH-ICS/CARV
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# Panagiotis Peristerakis <perister@ics.forth.gr>
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#
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#for more infos, check out /platform/template/config.mk
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PLATFORM_RISCV_XLEN = 64
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# Blobs to build
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FW_TEXT_START=0x80000000
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FW_JUMP=n
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_JUMP_ADDR=0x80400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_JUMP_ADDR=0x80200000
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endif
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FW_JUMP_FDT_ADDR=0x82200000
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# Firmware with payload configuration.
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FW_PAYLOAD=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_PAYLOAD_OFFSET=0x400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_PAYLOAD_OFFSET=0x200000
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endif
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FW_PAYLOAD_FDT_ADDR=0x82200000
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FW_PAYLOAD_ALIGN=0x1000
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8
platform/fpga/ariane/objects.mk
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8
platform/fpga/ariane/objects.mk
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (C) 2019 FORTH-ICS/CARV
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# Panagiotis Peristerakis <perister@ics.forth.gr>
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#
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platform-objs-y += platform.o
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206
platform/fpga/ariane/platform.c
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206
platform/fpga/ariane/platform.c
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2019 FORTH-ICS/CARV
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* Panagiotis Peristerakis <perister@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/sys/clint.h>
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#define ARIANE_UART_ADDR 0x10000000
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#define ARIANE_UART_FREQ 50000000
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#define ARIANE_UART_BAUDRATE 115200
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#define ARIANE_UART_REG_SHIFT 2
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#define ARIANE_UART_REG_WIDTH 4
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#define ARIANE_PLIC_ADDR 0xc000000
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#define ARIANE_PLIC_NUM_SOURCES 3
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#define ARIANE_HART_COUNT 1
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#define ARIANE_CLINT_ADDR 0x2000000
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#define PLIC_ENABLE_BASE 0x2000
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#define PLIC_ENABLE_STRIDE 0x80
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#define PLIC_CONTEXT_BASE 0x200000
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#define PLIC_CONTEXT_STRIDE 0x1000
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#define SBI_ARIANE_FEATURES \
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(SBI_PLATFORM_HAS_TIMER_VALUE | \
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SBI_PLATFORM_HAS_SCOUNTEREN | \
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SBI_PLATFORM_HAS_MCOUNTEREN | \
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SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
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/*
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* Ariane platform early initialization.
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*/
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static int ariane_early_init(bool cold_boot)
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{
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/* For now nothing to do. */
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return 0;
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}
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/*
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* Ariane platform final initialization.
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*/
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static int ariane_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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fdt_fixups(fdt);
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return 0;
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}
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/*
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* Initialize the ariane console.
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*/
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static int ariane_console_init(void)
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{
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return uart8250_init(ARIANE_UART_ADDR,
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ARIANE_UART_FREQ,
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ARIANE_UART_BAUDRATE,
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ARIANE_UART_REG_SHIFT,
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ARIANE_UART_REG_WIDTH);
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}
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static int plic_ariane_warm_irqchip_init(u32 target_hart,
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int m_cntx_id, int s_cntx_id)
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{
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size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1;
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if (ARIANE_HART_COUNT <= target_hart)
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return -1;
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/* By default, enable all IRQs for M-mode of target HART */
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if (m_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(m_cntx_id, i, 1);
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}
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/* Enable all IRQs for S-mode of target HART */
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if (s_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(s_cntx_id, i, 1);
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}
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/* By default, enable M-mode threshold */
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if (m_cntx_id > -1)
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plic_set_thresh(m_cntx_id, 1);
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/* By default, disable S-mode threshold */
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if (s_cntx_id > -1)
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plic_set_thresh(s_cntx_id, 0);
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return 0;
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}
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/*
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* Initialize the ariane interrupt controller for current HART.
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*/
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static int ariane_irqchip_init(bool cold_boot)
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{
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(ARIANE_PLIC_ADDR,
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ARIANE_PLIC_NUM_SOURCES,
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ARIANE_HART_COUNT);
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if (ret)
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return ret;
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}
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return plic_ariane_warm_irqchip_init(hartid,
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2 * hartid, 2 * hartid + 1);
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}
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/*
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* Initialize IPI for current HART.
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*/
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static int ariane_ipi_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_ipi_init(ARIANE_CLINT_ADDR,
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ARIANE_HART_COUNT);
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if (ret)
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return ret;
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}
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return clint_warm_ipi_init();
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}
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/*
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* Initialize ariane timer for current HART.
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*/
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static int ariane_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_timer_init(ARIANE_CLINT_ADDR,
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ARIANE_HART_COUNT, TRUE);
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if (ret)
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return ret;
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}
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return clint_warm_timer_init();
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}
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/*
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* Reboot the ariane.
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*/
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static int ariane_system_reboot(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System reboot\n");
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return 0;
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}
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/*
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* Shutdown or poweroff the ariane.
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*/
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static int ariane_system_shutdown(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System shutdown\n");
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return 0;
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}
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/*
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* Platform descriptor.
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*/
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const struct sbi_platform_operations platform_ops = {
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.early_init = ariane_early_init,
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.final_init = ariane_final_init,
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.console_init = ariane_console_init,
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.console_putc = uart8250_putc,
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.console_getc = uart8250_getc,
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.irqchip_init = ariane_irqchip_init,
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.ipi_init = ariane_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.timer_init = ariane_timer_init,
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.timer_value = clint_timer_value,
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.timer_event_start = clint_timer_event_start,
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.timer_event_stop = clint_timer_event_stop,
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.system_reboot = ariane_system_reboot,
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.system_shutdown = ariane_system_shutdown
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "ARIANE RISC-V",
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.features = SBI_ARIANE_FEATURES,
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.hart_count = ARIANE_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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