forked from Mirrors/opensbi
lib: utils/cppc: Add RPMI CPPC driver
Add RPMI based driver for CPPC register read, write and probe. Signed-off-by: Subrahmanya Lingappa <slingappa@ventanamicro.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Co-developed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
This commit is contained in:
Subrahmanya Lingappa
committed by
Anup Patel
Anup Patel
parent
54e632b72e
commit
591a98bdd5
@@ -7,4 +7,13 @@ config FDT_CPPC
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depends on FDT
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default n
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if FDT_CPPC
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config FDT_CPPC_RPMI
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bool "FDT RPMI CPPC driver"
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depends on FDT_MAILBOX && RPMI_MAILBOX
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default n
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endif
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endmenu
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377
lib/utils/cppc/fdt_cppc_rpmi.c
Normal file
377
lib/utils/cppc/fdt_cppc_rpmi.c
Normal file
@@ -0,0 +1,377 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2024 Ventana Micro Systems Inc.
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*
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* Authors:
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* Subrahmanya Lingappa <slingappa@ventanamicro.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_cppc.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi_utils/cppc/fdt_cppc.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/mailbox/fdt_mailbox.h>
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#include <sbi_utils/mailbox/rpmi_mailbox.h>
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/**
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* Per hart RPMI CPPC fast channel size (bytes)
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* PASSIVE MODE:
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* 0x0: DESIRED_PERFORMANCE (4-byte)
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* 0x4: __RESERVED (4-byte)
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* ACTIVE MODE: (not supported yet)
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* 0x0: MINIMUM PERFORMANCE (4-byte)
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* 0x4: MAXIMUM PERFORMANCE (4-byte)
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*/
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#define RPMI_CPPC_HART_FASTCHAN_SIZE 0x8
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struct rpmi_cppc {
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struct mbox_chan *chan;
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bool fc_supported;
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bool fc_db_supported;
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enum rpmi_cppc_fast_channel_db_width fc_db_width;
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enum rpmi_cppc_fast_channel_cppc_mode mode;
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ulong fc_perf_request_addr;
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ulong fc_perf_feedback_addr;
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ulong fc_db_addr;
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u64 fc_db_setmask;
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u64 fc_db_preservemask;
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};
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static unsigned long rpmi_cppc_offset;
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static struct rpmi_cppc *rpmi_cppc_get_pointer(u32 hartid)
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{
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struct sbi_scratch *scratch;
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scratch = sbi_hartid_to_scratch(hartid);
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if (!scratch || !rpmi_cppc_offset)
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return NULL;
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return sbi_scratch_offset_ptr(scratch, rpmi_cppc_offset);
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}
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static void rpmi_cppc_fc_db_trigger(struct rpmi_cppc *cppc)
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{
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u8 db_val_u8 = 0;
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u16 db_val_u16 = 0;
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u32 db_val_u32 = 0;
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switch (cppc->fc_db_width) {
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case RPMI_CPPC_FAST_CHANNEL_DB_WIDTH_8:
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db_val_u8 = readb((void *)cppc->fc_db_addr);
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db_val_u8 = (u8)cppc->fc_db_setmask |
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(db_val_u8 & (u8)cppc->fc_db_preservemask);
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writeb(db_val_u8, (void *)cppc->fc_db_addr);
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break;
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case RPMI_CPPC_FAST_CHANNEL_DB_WIDTH_16:
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db_val_u16 = readw((void *)cppc->fc_db_addr);
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db_val_u16 = (u16)cppc->fc_db_setmask |
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(db_val_u16 & (u16)cppc->fc_db_preservemask);
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writew(db_val_u16, (void *)cppc->fc_db_addr);
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break;
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case RPMI_CPPC_FAST_CHANNEL_DB_WIDTH_32:
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db_val_u32 = readl((void *)cppc->fc_db_addr);
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db_val_u32 = (u32)cppc->fc_db_setmask |
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(db_val_u32 & (u32)cppc->fc_db_preservemask);
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writel(db_val_u32, (void *)cppc->fc_db_addr);
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break;
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case RPMI_CPPC_FAST_CHANNEL_DB_WIDTH_64:
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#if __riscv_xlen != 32
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u64 db_val_u64 = 0;
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db_val_u64 = readq((void *)cppc->fc_db_addr);
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db_val_u64 = cppc->fc_db_setmask |
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(db_val_u64 & cppc->fc_db_preservemask);
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writeq(db_val_u64, (void *)cppc->fc_db_addr);
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#else
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u32 db_val_u32_hi = 0;
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db_val_u32 = readl((void *)cppc->fc_db_addr);
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db_val_u32_hi = readl((void *)(cppc->fc_db_addr + 4));
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db_val_u32 = (u32)cppc->fc_db_setmask |
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(db_val_u32 & (u32)cppc->fc_db_preservemask);
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db_val_u32_hi = (u32)(cppc->fc_db_setmask >> 32) |
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(db_val_u32 & (u32)(cppc->fc_db_preservemask >> 32));
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writel(db_val_u32, (void *)cppc->fc_db_addr);
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writel(db_val_u32_hi, (void *)(cppc->fc_db_addr + 4));
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#endif
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break;
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default:
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break;
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}
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}
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static int rpmi_cppc_read(unsigned long reg, u64 *val)
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{
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int rc = SBI_SUCCESS;
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struct rpmi_cppc_read_reg_req req;
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struct rpmi_cppc_read_reg_resp resp;
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struct rpmi_cppc *cppc;
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req.hart_id = current_hartid();
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req.reg_id = reg;
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cppc = rpmi_cppc_get_pointer(req.hart_id);
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rc = rpmi_normal_request_with_status(
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cppc->chan, RPMI_CPPC_SRV_READ_REG,
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&req, rpmi_u32_count(req), rpmi_u32_count(req),
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&resp, rpmi_u32_count(resp), rpmi_u32_count(resp));
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if (rc)
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return rc;
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#if __riscv_xlen == 32
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*val = resp.data_lo;
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#else
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*val = (u64)resp.data_hi << 32 | resp.data_lo;
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#endif
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return rc;
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}
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static int rpmi_cppc_write(unsigned long reg, u64 val)
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{
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int rc = SBI_SUCCESS;
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u32 hart_id = current_hartid();
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struct rpmi_cppc_write_reg_req req;
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struct rpmi_cppc_write_reg_resp resp;
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struct rpmi_cppc *cppc = rpmi_cppc_get_pointer(hart_id);
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if (reg != SBI_CPPC_DESIRED_PERF || !cppc->fc_supported) {
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req.hart_id = hart_id;
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req.reg_id = reg;
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req.data_lo = val & 0xFFFFFFFF;
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req.data_hi = val >> 32;
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rc = rpmi_normal_request_with_status(
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cppc->chan, RPMI_CPPC_SRV_WRITE_REG,
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&req, rpmi_u32_count(req), rpmi_u32_count(req),
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&resp, rpmi_u32_count(resp), rpmi_u32_count(resp));
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} else {
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/* use fast path writes for desired_perf in passive mode */
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writel((u32)val, (void *)cppc->fc_perf_request_addr);
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if (cppc->fc_db_supported)
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rpmi_cppc_fc_db_trigger(cppc);
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}
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return rc;
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}
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static int rpmi_cppc_probe(unsigned long reg)
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{
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int rc;
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struct rpmi_cppc *cppc;
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struct rpmi_cppc_probe_resp resp;
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struct rpmi_cppc_probe_req req;
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req.hart_id = current_hartid();
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req.reg_id = reg;
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cppc = rpmi_cppc_get_pointer(req.hart_id);
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if (!cppc)
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return SBI_ENOSYS;
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rc = rpmi_normal_request_with_status(
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cppc->chan, RPMI_CPPC_SRV_PROBE_REG,
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&req, rpmi_u32_count(req), rpmi_u32_count(req),
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&resp, rpmi_u32_count(resp), rpmi_u32_count(resp));
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if (rc)
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return rc;
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return resp.reg_len;
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}
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static struct sbi_cppc_device sbi_rpmi_cppc = {
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.name = "rpmi-cppc",
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.cppc_read = rpmi_cppc_read,
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.cppc_write = rpmi_cppc_write,
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.cppc_probe = rpmi_cppc_probe,
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};
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static int rpmi_cppc_update_hart_scratch(struct mbox_chan *chan)
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{
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int rc, i;
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bool fc_supported = false;
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bool fc_db_supported = false;
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struct rpmi_cppc_hart_list_req req;
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struct rpmi_cppc_hart_list_resp resp;
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struct rpmi_cppc_get_fastchan_offset_req hfreq;
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struct rpmi_cppc_get_fastchan_offset_resp hfresp;
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struct rpmi_cppc_get_fastchan_region_resp fresp;
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enum rpmi_cppc_fast_channel_db_width fc_db_width = 0;
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enum rpmi_cppc_fast_channel_cppc_mode cppc_mode = 0;
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struct rpmi_cppc *cppc;
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unsigned long fc_region_addr = 0;
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unsigned long fc_region_size = 0;
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unsigned long fc_db_addr = 0;
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u64 fc_db_setmask = 0;
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u64 fc_db_preservemask = 0;
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rc = rpmi_normal_request_with_status(
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chan, RPMI_CPPC_SRV_GET_FAST_CHANNEL_REGION,
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NULL, 0, 0,
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&fresp, rpmi_u32_count(fresp), rpmi_u32_count(fresp));
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if (rc && rc != SBI_ENOTSUPP)
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return rc;
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/* At this point fast channel availability is confirmed */
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fc_supported = (rc != SBI_ENOTSUPP)? true : false;
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/* If fast channel is supported, add the fast channel
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* region in root domain as MMIO RW. And, get the doorbell
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* information from the response */
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if (fc_supported) {
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#if __riscv_xlen == 32
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fc_region_addr = fresp.region_addr_lo;
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fc_region_size = fresp.region_size_lo;
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fc_db_addr = fresp.db_addr_lo;
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#else
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fc_region_addr = (ulong)fresp.region_addr_hi << 32 |
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fresp.region_addr_lo;
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fc_region_size = (ulong)fresp.region_size_hi << 32 |
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fresp.region_size_lo;
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fc_db_addr = (ulong)fresp.db_addr_hi << 32 | fresp.db_addr_lo;
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#endif
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rc = sbi_domain_root_add_memrange(fc_region_addr,
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fc_region_size,
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RPMI_CPPC_HART_FASTCHAN_SIZE,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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cppc_mode = (fresp.flags & RPMI_CPPC_FAST_CHANNEL_CPPC_MODE_MASK) >>
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RPMI_CPPC_FAST_CHANNEL_CPPC_MODE_POS;
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fc_db_supported = fresp.flags &
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RPMI_CPPC_FAST_CHANNEL_FLAGS_DB_SUPPORTED;
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fc_db_width = (fresp.flags &
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RPMI_CPPC_FAST_CHANNEL_FLAGS_DB_WIDTH_MASK) >>
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RPMI_CPPC_FAST_CHANNEL_FLAGS_DB_WIDTH_POS;
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fc_db_setmask = (u64)fresp.db_setmask_hi << 32 |
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fresp.db_setmask_lo;
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fc_db_preservemask = (u64)fresp.db_preservemask_hi << 32 |
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fresp.db_preservemask_lo;
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}
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/* Get the hart list and depending on the fast channel support
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* initialize the per hart cppc structure */
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req.start_index = 0;
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do {
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rc = rpmi_normal_request_with_status(
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chan, RPMI_CPPC_SRV_GET_HART_LIST,
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&req, rpmi_u32_count(req), rpmi_u32_count(req),
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&resp, rpmi_u32_count(resp), rpmi_u32_count(resp));
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if (rc)
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return rc;
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/* For each returned harts, get their fastchan offset and
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* complete the initialization of per hart cppc structure */
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for (i = 0; i < resp.returned; i++) {
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cppc = rpmi_cppc_get_pointer(resp.hartid[i]);
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if (!cppc)
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return SBI_ENOSYS;
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cppc->chan = chan;
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cppc->mode = cppc_mode;
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cppc->fc_supported = fc_supported;
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if (fc_supported) {
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hfreq.hart_id = resp.hartid[i];
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rc = rpmi_normal_request_with_status(
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chan,
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RPMI_CPPC_SRV_GET_FAST_CHANNEL_OFFSET,
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&hfreq,
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rpmi_u32_count(hfreq),
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rpmi_u32_count(hfreq),
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&hfresp,
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rpmi_u32_count(hfresp),
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rpmi_u32_count(hfresp));
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if (rc)
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continue;
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#if __riscv_xlen == 32
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cppc->fc_perf_request_addr = fc_region_addr +
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hfresp.fc_perf_request_offset_lo;
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cppc->fc_perf_feedback_addr = fc_region_addr +
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hfresp.fc_perf_feedback_offset_lo;
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#else
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cppc->fc_perf_request_addr = fc_region_addr +
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((ulong)hfresp.fc_perf_request_offset_hi << 32 |
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hfresp.fc_perf_request_offset_lo);
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cppc->fc_perf_feedback_addr = fc_region_addr +
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((ulong)hfresp.fc_perf_feedback_offset_hi << 32 |
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hfresp.fc_perf_feedback_offset_lo);
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#endif
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cppc->fc_db_supported = fc_db_supported;
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cppc->fc_db_addr = fc_db_addr;
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cppc->fc_db_width = fc_db_width;
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cppc->fc_db_setmask = fc_db_setmask;
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cppc->fc_db_preservemask = fc_db_preservemask;
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}
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else {
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cppc->fc_perf_request_addr = 0;
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cppc->fc_perf_feedback_addr = 0;
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cppc->fc_db_supported = 0;
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cppc->fc_db_addr = 0;
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cppc->fc_db_width = 0;
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cppc->fc_db_setmask = 0;
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cppc->fc_db_preservemask = 0;
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}
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}
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req.start_index += resp.returned;
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} while (resp.remaining);
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return 0;
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}
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static int rpmi_cppc_cold_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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int rc;
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struct mbox_chan *chan;
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if (!rpmi_cppc_offset) {
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rpmi_cppc_offset =
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sbi_scratch_alloc_type_offset(struct rpmi_cppc);
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if (!rpmi_cppc_offset)
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return SBI_ENOMEM;
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}
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/*
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* If channel request failed then other end does not support
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* CPPC service group so do nothing.
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*/
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rc = fdt_mailbox_request_chan(fdt, nodeoff, 0, &chan);
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if (rc)
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return SBI_ENODEV;
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/* Update per-HART scratch space */
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rc = rpmi_cppc_update_hart_scratch(chan);
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if (rc)
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return rc;
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sbi_cppc_set_device(&sbi_rpmi_cppc);
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return 0;
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}
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static const struct fdt_match rpmi_cppc_match[] = {
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{ .compatible = "riscv,rpmi-cppc" },
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{},
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};
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struct fdt_driver fdt_cppc_rpmi = {
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.match_table = rpmi_cppc_match,
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.init = rpmi_cppc_cold_init,
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};
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@@ -9,3 +9,6 @@
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libsbiutils-objs-$(CONFIG_FDT_CPPC) += cppc/fdt_cppc.o
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libsbiutils-objs-$(CONFIG_FDT_CPPC) += cppc/fdt_cppc_drivers.carray.o
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carray-fdt_cppc_drivers-$(CONFIG_FDT_CPPC_RPMI) += fdt_cppc_rpmi
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libsbiutils-objs-$(CONFIG_FDT_CPPC_RPMI) += cppc/fdt_cppc_rpmi.o
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