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platform: include: andes45: Add PMU related CSR defines

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Add CSR definitions for Andes PMU extension.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This commit is contained in:
Yu Chien Peter Lin
2023-11-30 20:42:03 +08:00
committed by Anup Patel
parent a48f2cfd94
commit 51ec60c9ea
1 changed files with 26 additions and 0 deletions
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26
platform/generic/include/andes/andes45.h
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@@ -12,6 +12,17 @@
#define CSR_MDCM_CFG 0xfc1
#define CSR_MMSC_CFG 0xfc2
/* Machine Trap Related Registers */
#define CSR_MSLIDELEG 0x7d5
/* Counter Related Registers */
#define CSR_MCOUNTERWEN 0x7ce
#define CSR_MCOUNTERINTEN 0x7cf
#define CSR_MCOUNTERMASK_M 0x7d1
#define CSR_MCOUNTERMASK_S 0x7d2
#define CSR_MCOUNTERMASK_U 0x7d3
#define CSR_MCOUNTEROVF 0x7d4
#define MICM_CFG_ISZ_OFFSET 6
#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
@@ -26,4 +37,19 @@
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
/* Performance monitor */
#define MMSC_CFG_PMNDS_MASK (1 << 15)
#define MIP_PMOVI (1 << 18)
#ifndef __ASSEMBLER__
#define has_andes_pmu() \
({ \
(((csr_read(CSR_MMSC_CFG) & \
MMSC_CFG_PMNDS_MASK) \
&& misa_extension('S')) ? true : false); \
})
#endif /* __ASSEMBLER__ */
#endif /* _RISCV_ANDES45_H */