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platform: Remove PLAT_HART_COUNT and PLAT_HART_STACK_SIZE

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The PLAT_HART_COUNT and PLAT_HART_STACK_SIZE are only used
by platform code so no need of exposing these to everyone
by adding it to platform-cppflags-y.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
2018-12-22 21:01:40 +05:30
committed by Anup Patel
parent 58ca525a7d
commit 472d3f4e17
9 changed files with 40 additions and 40 deletions
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5
platform/kendryte/k210/config.mk
View File

@@ -7,11 +7,8 @@
# SPDX-License-Identifier: BSD-2-Clause
#
# Essential defines required by SBI platform
platform-cppflags-y+= -DPLAT_HART_COUNT=2
platform-cppflags-y+= -DPLAT_HART_STACK_SIZE=4096
# Compiler flags
platform-cppflags-y =
platform-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-ldflags-y =

10
platform/kendryte/k210/platform.c
View File

@@ -38,7 +38,7 @@ static char k210_console_getc(void)
static int k210_cold_irqchip_init(void)
{
return plic_cold_irqchip_init(PLIC_BASE_ADDR, PLIC_NUM_SOURCES,
PLAT_HART_COUNT);
K210_HART_COUNT);
}
static int k210_warm_irqchip_init(u32 core_id)
@@ -50,12 +50,12 @@ static int k210_warm_irqchip_init(u32 core_id)
static int k210_cold_ipi_init(void)
{
return clint_cold_ipi_init(CLINT_BASE_ADDR, PLAT_HART_COUNT);
return clint_cold_ipi_init(CLINT_BASE_ADDR, K210_HART_COUNT);
}
static int k210_cold_timer_init(void)
{
return clint_cold_timer_init(CLINT_BASE_ADDR, PLAT_HART_COUNT);
return clint_cold_timer_init(CLINT_BASE_ADDR, K210_HART_COUNT);
}
static int k210_system_reboot(u32 type)
@@ -79,8 +79,8 @@ struct sbi_platform platform = {
.name = "Kendryte K210",
.features = SBI_PLATFORM_HAS_MMIO_TIMER_VALUE,
.hart_count = PLAT_HART_COUNT,
.hart_stack_size = PLAT_HART_STACK_SIZE,
.hart_count = K210_HART_COUNT,
.hart_stack_size = K210_HART_STACK_SIZE,
.disabled_hart_mask = 0,
.console_init = k210_console_init,

5
platform/kendryte/k210/platform.h
View File

@@ -18,12 +18,15 @@
#include <sbi/riscv_asm.h>
#define K210_HART_COUNT 2
#define K210_HART_STACK_SIZE 4096
/* Register base address */
/* Under Coreplex */
#define CLINT_BASE_ADDR (0x02000000U)
#define PLIC_BASE_ADDR (0x0C000000U)
#define PLIC_NUM_CORES (PLAT_HART_COUNT)
#define PLIC_NUM_CORES (K210_HART_COUNT)
/* Under TileLink */
#define GPIOHS_BASE_ADDR (0x38001000U)