forked from Mirrors/opensbi
lib: Extend trap redirection for hypervisor v0.5 spec
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
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@@ -22,12 +22,12 @@ union reg_data {
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};
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int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch)
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{
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union reg_data val;
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struct sbi_trap_info uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, fp = 0, shift = 0, len = 0;
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ulong insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
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@@ -101,6 +101,8 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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uptrap.epc = regs->mepc;
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uptrap.cause = mcause;
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uptrap.tval = addr;
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uptrap.tval2 = tval2;
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uptrap.tinst = tinst;
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return sbi_trap_redirect(regs, &uptrap, scratch);
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}
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@@ -129,12 +131,12 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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}
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int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch)
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{
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union reg_data val;
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struct sbi_trap_info uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, len = 0;
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ulong insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
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@@ -199,6 +201,8 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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uptrap.epc = regs->mepc;
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uptrap.cause = mcause;
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uptrap.tval = addr;
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uptrap.tval2 = tval2;
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uptrap.tinst = tinst;
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return sbi_trap_redirect(regs, &uptrap, scratch);
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}
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