forked from Mirrors/opensbi
lib: sbi: Add PMU support
RISC-V SBI v0.3 specification defined a PMU extension to configure/start/stop the hardware/firmware pmu events. Implement PMU support in OpenSBI library. The implementation is agnostic of event to counter mapping & mhpmevent value configuration. That means, it expects platform hooks will be used to set up the mapping and provide the mhpmevent value at runtime. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra
@@ -28,6 +28,7 @@
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#define SBI_EXT_RFENCE 0x52464E43
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#define SBI_EXT_HSM 0x48534D
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#define SBI_EXT_SRST 0x53525354
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#define SBI_EXT_PMU 0x504D55
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/* SBI function IDs for BASE extension*/
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#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
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@@ -91,6 +92,139 @@
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#define SBI_SRST_RESET_REASON_NONE 0x0
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#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
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/* SBI function IDs for PMU extension */
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#define SBI_EXT_PMU_NUM_COUNTERS 0x0
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#define SBI_EXT_PMU_COUNTER_GET_INFO 0x1
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#define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2
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#define SBI_EXT_PMU_COUNTER_START 0x3
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#define SBI_EXT_PMU_COUNTER_STOP 0x4
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#define SBI_EXT_PMU_COUNTER_FW_READ 0x5
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/** General pmu event codes specified in SBI PMU extension */
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enum sbi_pmu_hw_generic_events_t {
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SBI_PMU_HW_NO_EVENT = 0,
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SBI_PMU_HW_CPU_CYCLES = 1,
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SBI_PMU_HW_INSTRUCTIONS = 2,
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SBI_PMU_HW_CACHE_REFERENCES = 3,
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SBI_PMU_HW_CACHE_MISSES = 4,
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SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
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SBI_PMU_HW_BRANCH_MISSES = 6,
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SBI_PMU_HW_BUS_CYCLES = 7,
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SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
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SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
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SBI_PMU_HW_REF_CPU_CYCLES = 10,
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SBI_PMU_HW_GENERAL_MAX,
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};
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/**
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* Generalized hardware cache events:
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*
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* { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
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* { read, write, prefetch } x
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* { accesses, misses }
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*/
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enum sbi_pmu_hw_cache_id {
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SBI_PMU_HW_CACHE_L1D = 0,
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SBI_PMU_HW_CACHE_L1I = 1,
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SBI_PMU_HW_CACHE_LL = 2,
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SBI_PMU_HW_CACHE_DTLB = 3,
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SBI_PMU_HW_CACHE_ITLB = 4,
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SBI_PMU_HW_CACHE_BPU = 5,
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SBI_PMU_HW_CACHE_NODE = 6,
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SBI_PMU_HW_CACHE_MAX,
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};
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enum sbi_pmu_hw_cache_op_id {
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SBI_PMU_HW_CACHE_OP_READ = 0,
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SBI_PMU_HW_CACHE_OP_WRITE = 1,
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SBI_PMU_HW_CACHE_OP_PREFETCH = 2,
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SBI_PMU_HW_CACHE_OP_MAX,
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};
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enum sbi_pmu_hw_cache_op_result_id {
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SBI_PMU_HW_CACHE_RESULT_ACCESS = 0,
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SBI_PMU_HW_CACHE_RESULT_MISS = 1,
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SBI_PMU_HW_CACHE_RESULT_MAX,
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};
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/**
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* Special "firmware" events provided by the OpenSBI, even if the hardware
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* does not support performance events. These events are encoded as a raw
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* event type in Linux kernel perf framework.
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*/
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enum sbi_pmu_fw_event_code_id {
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SBI_PMU_FW_MISALIGNED_LOAD = 0,
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SBI_PMU_FW_MISALIGNED_STORE = 1,
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SBI_PMU_FW_ACCESS_LOAD = 2,
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SBI_PMU_FW_ACCESS_STORE = 3,
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SBI_PMU_FW_ILLEGAL_INSN = 4,
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SBI_PMU_FW_SET_TIMER = 5,
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SBI_PMU_FW_IPI_SENT = 6,
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SBI_PMU_FW_IPI_RECVD = 7,
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SBI_PMU_FW_FENCE_I_SENT = 8,
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SBI_PMU_FW_FENCE_I_RECVD = 9,
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SBI_PMU_FW_SFENCE_VMA_SENT = 10,
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SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
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SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
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SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
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SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
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SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
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SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
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SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
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SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
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SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
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SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
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SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
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SBI_PMU_FW_MAX,
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};
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/** SBI PMU event idx type */
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enum sbi_pmu_event_type_id {
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SBI_PMU_EVENT_TYPE_HW = 0x0,
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SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1,
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SBI_PMU_EVENT_TYPE_HW_RAW = 0x2,
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SBI_PMU_EVENT_TYPE_FW = 0xf,
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SBI_PMU_EVENT_TYPE_MAX,
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};
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/** SBI PMU counter type */
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enum sbi_pmu_ctr_type {
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SBI_PMU_CTR_TYPE_HW = 0,
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SBI_PMU_CTR_TYPE_FW,
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};
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/* Helper macros to decode event idx */
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#define SBI_PMU_EVENT_IDX_OFFSET 20
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#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
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#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
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#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
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#define SBI_PMU_EVENT_RAW_IDX 0x20000
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#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
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/* Flags defined for config matching function */
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#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
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#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
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#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
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#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
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#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
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#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
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#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
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#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
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/* Flags defined for counter start function */
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#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
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/* Flags defined for counter stop function */
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#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
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/* SBI base specification related macros */
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#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
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#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
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#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
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@@ -107,8 +241,10 @@
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#define SBI_ERR_DENIED -4
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#define SBI_ERR_INVALID_ADDRESS -5
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#define SBI_ERR_ALREADY_AVAILABLE -6
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#define SBI_ERR_ALREADY_STARTED -7
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#define SBI_ERR_ALREADY_STOPPED -8
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#define SBI_LAST_ERR SBI_ERR_ALREADY_AVAILABLE
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#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED
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/* clang-format on */
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