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all: run clang-format and update checked-in files

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Noisy commit, no functional changes.

Generated with an current upstream clang-format and:

clang-format -i $(find . -name \*.[ch])

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2019-04-10 17:41:52 -07:00
committed by Anup Patel
parent fbf986ac2a
commit 10baa64c02
59 changed files with 943 additions and 1004 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
lib/riscv_asm.c
View File

@@ -163,28 +163,26 @@ static unsigned long ctz(unsigned long x)
return ret;
}
int pmp_set(unsigned int n, unsigned long prot,
unsigned long addr, unsigned long log2len)
int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
unsigned long log2len)
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask, pmpcfg;
unsigned long addrmask, pmpaddr;
/* check parameters */
if (n >= PMP_COUNT ||
log2len > __riscv_xlen ||
log2len < PMP_SHIFT)
if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
return SBI_EINVAL;
/* calculate PMP register and offset */
/* calculate PMP register and offset */
#if __riscv_xlen == 32
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_shift = (n & 7) << 3;
#else
pmpcfg_csr = -1;
pmpcfg_csr = -1;
pmpcfg_shift = -1;
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
@@ -194,7 +192,7 @@ int pmp_set(unsigned int n, unsigned long prot,
/* encode PMP config */
prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
cfgmask = ~(0xff << pmpcfg_shift);
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
/* encode PMP address */
@@ -205,7 +203,7 @@ int pmp_set(unsigned int n, unsigned long prot,
pmpaddr = -1UL;
} else {
addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
pmpaddr |= (addrmask >> 1);
}
}
@@ -217,28 +215,27 @@ int pmp_set(unsigned int n, unsigned long prot,
return 0;
}
int pmp_get(unsigned int n, unsigned long *prot_out,
unsigned long *addr_out, unsigned long *log2len_out)
int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
unsigned long *log2len_out)
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask, pmpcfg, prot;
unsigned long t1, addr, log2len;
/* check parameters */
if (n >= PMP_COUNT || !prot_out ||
!addr_out || !log2len_out)
if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len_out)
return SBI_EINVAL;
*prot_out = *addr_out = *log2len_out = 0;
/* calculate PMP register and offset */
#if __riscv_xlen == 32
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_shift = (n & 7) << 3;
#else
pmpcfg_csr = -1;
pmpcfg_csr = -1;
pmpcfg_shift = -1;
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
@@ -247,28 +244,28 @@ int pmp_get(unsigned int n, unsigned long *prot_out,
/* decode PMP config */
cfgmask = (0xff << pmpcfg_shift);
pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
prot = pmpcfg >> pmpcfg_shift;
pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
prot = pmpcfg >> pmpcfg_shift;
/* decode PMP address */
if ((prot & PMP_A) == PMP_A_NAPOT) {
addr = csr_read_num(pmpaddr_csr);
if (addr == -1UL) {
addr = 0;
addr = 0;
log2len = __riscv_xlen;
} else {
t1 = ctz(~addr);
addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
t1 = ctz(~addr);
addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
log2len = (t1 + PMP_SHIFT + 1);
}
} else {
addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
log2len = PMP_SHIFT;
}
/* return details */
*prot_out = prot;
*addr_out = addr;
*prot_out = prot;
*addr_out = addr;
*log2len_out = log2len;
return 0;

211
lib/riscv_atomic.c
View File

@@ -30,11 +30,10 @@ long atomic_add_return(atomic_t *atom, long value)
{
long ret;
__asm__ __volatile__ (
" amoadd.w.aqrl %1, %2, %0"
: "+A" (atom->counter), "=r" (ret)
: "r" (value)
: "memory");
__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(value)
: "memory");
return ret + value;
}
@@ -43,99 +42,98 @@ long atomic_sub_return(atomic_t *atom, long value)
{
long ret;
__asm__ __volatile__ (
" amoadd.w.aqrl %1, %2, %0"
: "+A" (atom->counter), "=r" (ret)
: "r" (-value)
: "memory");
__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(-value)
: "memory");
return ret - value;
}
#define __xchg(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
"0: lr.w %0, %2\n" \
" sc.w.rl %1, %z3, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
: "rJ" (__new) \
: "memory"); \
break; \
case 8: \
__asm__ __volatile__ ( \
"0: lr.d %0, %2\n" \
" sc.d.rl %1, %z3, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
: "rJ" (__new) \
: "memory"); \
break; \
default: \
break; \
} \
__ret; \
})
#define __xchg(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
case 4: \
__asm__ __volatile__("0: lr.w %0, %2\n" \
" sc.w.rl %1, %z3, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
: "=&r"(__ret), "=&r"(__rc), \
"+A"(*__ptr) \
: "rJ"(__new) \
: "memory"); \
break; \
case 8: \
__asm__ __volatile__("0: lr.d %0, %2\n" \
" sc.d.rl %1, %z3, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
: "=&r"(__ret), "=&r"(__rc), \
"+A"(*__ptr) \
: "rJ"(__new) \
: "memory"); \
break; \
default: \
break; \
} \
__ret; \
})
#define xchg(ptr, n) \
({ \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __xchg((ptr), _n_, sizeof(*(ptr))); \
})
#define xchg(ptr, n) \
({ \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __xchg((ptr), _n_, sizeof(*(ptr))); \
})
#define __cmpxchg(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __old = (old); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
"0: lr.w %0, %2\n" \
" bne %0, %z3, 1f\n" \
" sc.w.rl %1, %z4, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
"1:\n" \
: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
: "rJ" (__old), "rJ" (__new) \
: "memory"); \
break; \
case 8: \
__asm__ __volatile__ ( \
"0: lr.d %0, %2\n" \
" bne %0, %z3, 1f\n" \
" sc.d.rl %1, %z4, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
"1:\n" \
: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
: "rJ" (__old), "rJ" (__new) \
: "memory"); \
break; \
default: \
break; \
} \
__ret; \
})
#define __cmpxchg(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __old = (old); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
case 4: \
__asm__ __volatile__("0: lr.w %0, %2\n" \
" bne %0, %z3, 1f\n" \
" sc.w.rl %1, %z4, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
"1:\n" \
: "=&r"(__ret), "=&r"(__rc), \
"+A"(*__ptr) \
: "rJ"(__old), "rJ"(__new) \
: "memory"); \
break; \
case 8: \
__asm__ __volatile__("0: lr.d %0, %2\n" \
" bne %0, %z3, 1f\n" \
" sc.d.rl %1, %z4, %2\n" \
" bnez %1, 0b\n" \
" fence rw, rw\n" \
"1:\n" \
: "=&r"(__ret), "=&r"(__rc), \
"+A"(*__ptr) \
: "rJ"(__old), "rJ"(__new) \
: "memory"); \
break; \
default: \
break; \
} \
__ret; \
})
#define cmpxchg(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), \
_o_, _n_, sizeof(*(ptr))); \
})
#define cmpxchg(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) \
__cmpxchg((ptr), _o_, _n_, sizeof(*(ptr))); \
})
long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
{
@@ -178,31 +176,30 @@ unsigned int atomic_raw_xchg_uint(volatile unsigned int *ptr,
}
#if (BITS_PER_LONG == 64)
#define __AMO(op) "amo" #op ".d"
#define __AMO(op) "amo" #op ".d"
#elif (BITS_PER_LONG == 32)
#define __AMO(op) "amo" #op ".w"
#define __AMO(op) "amo" #op ".w"
#else
#error "Unexpected BITS_PER_LONG"
#endif
#define __atomic_op_bit_ord(op, mod, nr, addr, ord) \
({ \
unsigned long __res, __mask; \
__mask = BIT_MASK(nr); \
__asm__ __volatile__ ( \
__AMO(op) #ord " %0, %2, %1" \
: "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \
: "r" (mod(__mask)) \
: "memory"); \
__res; \
})
#define __atomic_op_bit_ord(op, mod, nr, addr, ord) \
({ \
unsigned long __res, __mask; \
__mask = BIT_MASK(nr); \
__asm__ __volatile__(__AMO(op) #ord " %0, %2, %1" \
: "=r"(__res), "+A"(addr[BIT_WORD(nr)]) \
: "r"(mod(__mask)) \
: "memory"); \
__res; \
})
#define __atomic_op_bit(op, mod, nr, addr) \
#define __atomic_op_bit(op, mod, nr, addr) \
__atomic_op_bit_ord(op, mod, nr, addr, .aqrl)
/* Bitmask modifiers */
#define __NOP(x) (x)
#define __NOT(x) (~(x))
#define __NOP(x) (x)
#define __NOT(x) (~(x))
inline int atomic_raw_set_bit(int nr, volatile unsigned long *addr)
{

9
lib/riscv_locks.c
View File

@@ -19,11 +19,10 @@ int spin_trylock(spinlock_t *lock)
{
int tmp = 1, busy;
__asm__ __volatile__ (
" amoswap.w %0, %2, %1\n"
RISCV_ACQUIRE_BARRIER
: "=r" (busy), "+A" (lock->lock)
: "r" (tmp)
__asm__ __volatile__(
" amoswap.w %0, %2, %1\n" RISCV_ACQUIRE_BARRIER
: "=r"(busy), "+A"(lock->lock)
: "r"(tmp)
: "memory");
return !busy;

115
lib/sbi_console.c
View File

@@ -12,15 +12,12 @@
#include <sbi/riscv_locks.h>
static const struct sbi_platform *console_plat = NULL;
static spinlock_t console_out_lock = SPIN_LOCK_INITIALIZER;
static spinlock_t console_out_lock = SPIN_LOCK_INITIALIZER;
bool sbi_isprintable(char c)
{
if (((31 < c) && (c < 127)) ||
(c == '\f') ||
(c == '\r') ||
(c == '\n') ||
(c == '\t')) {
if (((31 < c) && (c < 127)) || (c == '\f') || (c == '\r') ||
(c == '\n') || (c == '\t')) {
return TRUE;
}
return FALSE;
@@ -54,22 +51,22 @@ void sbi_gets(char *s, int maxwidth, char endchar)
char *retval = s;
while ((ch = sbi_getc()) != endchar && ch >= 0 && maxwidth > 1) {
*retval = (char) ch;
*retval = (char)ch;
retval++;
maxwidth--;
}
*retval = '\0';
}
#define PAD_RIGHT 1
#define PAD_ZERO 2
#define PAD_ALTERNATE 4
#define PRINT_BUF_LEN 64
#define PAD_RIGHT 1
#define PAD_ZERO 2
#define PAD_ALTERNATE 4
#define PRINT_BUF_LEN 64
#define va_start(v,l) __builtin_va_start((v),l)
#define va_end __builtin_va_end
#define va_arg __builtin_va_arg
typedef __builtin_va_list va_list;
#define va_start(v, l) __builtin_va_start((v), l)
#define va_end __builtin_va_end
#define va_arg __builtin_va_arg
typedef __builtin_va_list va_list;
static void printc(char **out, u32 *out_len, char ch)
{
@@ -89,9 +86,10 @@ static void printc(char **out, u32 *out_len, char ch)
}
}
static int prints(char **out, u32 *out_len, const char *string, int width, int flags)
static int prints(char **out, u32 *out_len, const char *string, int width,
int flags)
{
int pc = 0;
int pc = 0;
char padchar = ' ';
if (width > 0) {
@@ -135,10 +133,10 @@ static int printi(char **out, u32 *out_len, long long i, int b, int sg,
if (sg && b == 10 && i < 0) {
neg = 1;
u = -i;
u = -i;
}
s = print_buf + PRINT_BUF_LEN - 1;
s = print_buf + PRINT_BUF_LEN - 1;
*s = '\0';
if (!u) {
@@ -211,59 +209,59 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
if (*format == 's') {
char *s = va_arg(args, char *);
acnt += sizeof(char *);
pc += prints(out, out_len,
s ? s : "(null)", width, flags);
pc += prints(out, out_len, s ? s : "(null)",
width, flags);
continue;
}
if ((*format == 'd') || (*format == 'i')) {
pc += printi(out, out_len,
va_arg(args, int),
10, 1, width, flags, '0');
pc += printi(out, out_len, va_arg(args, int),
10, 1, width, flags, '0');
acnt += sizeof(int);
continue;
}
if (*format == 'x') {
pc += printi(out, out_len,
va_arg(args, unsigned int),
16, 0, width, flags, 'a');
va_arg(args, unsigned int), 16, 0,
width, flags, 'a');
acnt += sizeof(unsigned int);
continue;
}
if (*format == 'X') {
pc += printi(out, out_len,
va_arg(args, unsigned int),
16, 0, width, flags, 'A');
va_arg(args, unsigned int), 16, 0,
width, flags, 'A');
acnt += sizeof(unsigned int);
continue;
}
if (*format == 'u') {
pc += printi(out, out_len,
va_arg(args, unsigned int),
10, 0, width, flags, 'a');
va_arg(args, unsigned int), 10, 0,
width, flags, 'a');
acnt += sizeof(unsigned int);
continue;
}
if (*format == 'p') {
pc += printi(out, out_len,
va_arg(args, unsigned long),
16, 0, width, flags, 'a');
va_arg(args, unsigned long), 16, 0,
width, flags, 'a');
acnt += sizeof(unsigned long);
continue;
}
if (*format == 'P') {
pc += printi(out, out_len,
va_arg(args, unsigned long),
16, 0, width, flags, 'A');
va_arg(args, unsigned long), 16, 0,
width, flags, 'A');
acnt += sizeof(unsigned long);
continue;
}
if (*format == 'l' && *(format + 1) == 'l') {
while (acnt & (sizeof(unsigned long long)-1)) {
while (acnt &
(sizeof(unsigned long long) - 1)) {
va_arg(args, int);
acnt += sizeof(int);
}
if (sizeof(unsigned long long) ==
sizeof(unsigned long)) {
sizeof(unsigned long)) {
tmp = va_arg(args, unsigned long long);
acnt += sizeof(unsigned long long);
} else {
@@ -271,48 +269,51 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
va_arg(args, unsigned long);
((unsigned long *)&tmp)[1] =
va_arg(args, unsigned long);
acnt += 2*sizeof(unsigned long);
acnt += 2 * sizeof(unsigned long);
}
if (*(format + 2) == 'u') {
format += 2;
pc += printi(out, out_len, tmp,
10, 0, width, flags, 'a');
pc += printi(out, out_len, tmp, 10, 0,
width, flags, 'a');
} else if (*(format + 2) == 'x') {
format += 2;
pc += printi(out, out_len, tmp,
16, 0, width, flags, 'a');
pc += printi(out, out_len, tmp, 16, 0,
width, flags, 'a');
} else if (*(format + 2) == 'X') {
format += 2;
pc += printi(out, out_len, tmp,
16, 0, width, flags, 'A');
pc += printi(out, out_len, tmp, 16, 0,
width, flags, 'A');
} else {
format += 1;
pc += printi(out, out_len, tmp,
10, 1, width, flags, '0');
pc += printi(out, out_len, tmp, 10, 1,
width, flags, '0');
}
continue;
} else if (*format == 'l') {
if (*(format + 1) == 'u') {
format += 1;
pc += printi(out, out_len,
va_arg(args, unsigned long),
10, 0, width, flags, 'a');
pc += printi(
out, out_len,
va_arg(args, unsigned long), 10,
0, width, flags, 'a');
} else if (*(format + 1) == 'x') {
format += 1;
pc += printi(out, out_len,
va_arg(args, unsigned long),
16, 0, width, flags, 'a');
pc += printi(
out, out_len,
va_arg(args, unsigned long), 16,
0, width, flags, 'a');
acnt += sizeof(unsigned long);
} else if (*(format + 1) == 'X') {
format += 1;
pc += printi(out, out_len,
va_arg(args, unsigned long),
16, 0, width, flags, 'A');
pc += printi(
out, out_len,
va_arg(args, unsigned long), 16,
0, width, flags, 'A');
acnt += sizeof(unsigned long);
} else {
pc += printi(out, out_len,
va_arg(args, long),
10, 1, width, flags, '0');
va_arg(args, long), 10, 1,
width, flags, '0');
acnt += sizeof(long);
}
}
@@ -325,7 +326,7 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
continue;
}
} else {
out:
out:
printc(out, out_len, *format);
++pc;
}

26
lib/sbi_ecall.c
View File

@@ -16,8 +16,8 @@
#include <sbi/sbi_timer.h>
#include <sbi/sbi_trap.h>
#define SBI_ECALL_VERSION_MAJOR 0
#define SBI_ECALL_VERSION_MINOR 1
#define SBI_ECALL_VERSION_MAJOR 0
#define SBI_ECALL_VERSION_MINOR 1
u16 sbi_ecall_version_major(void)
{
@@ -29,8 +29,7 @@ u16 sbi_ecall_version_minor(void)
return SBI_ECALL_VERSION_MINOR;
}
int sbi_ecall_handler(u32 hartid, ulong mcause,
struct sbi_trap_regs *regs,
int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
struct sbi_scratch *scratch)
{
int ret = SBI_ENOTSUPP;
@@ -40,7 +39,7 @@ int sbi_ecall_handler(u32 hartid, ulong mcause,
case SBI_ECALL_SET_TIMER:
#if __riscv_xlen == 32
sbi_timer_event_start(scratch,
(((u64)regs->a1 << 32) | (u64)regs->a0));
(((u64)regs->a1 << 32) | (u64)regs->a0));
#else
sbi_timer_event_start(scratch, (u64)regs->a0);
#endif
@@ -52,7 +51,7 @@ int sbi_ecall_handler(u32 hartid, ulong mcause,
break;
case SBI_ECALL_CONSOLE_GETCHAR:
regs->a0 = sbi_getc();
ret = 0;
ret = 0;
break;
case SBI_ECALL_CLEAR_IPI:
sbi_ipi_clear_smode(scratch);
@@ -68,20 +67,21 @@ int sbi_ecall_handler(u32 hartid, ulong mcause,
break;
case SBI_ECALL_REMOTE_SFENCE_VMA:
tlb_info.start = (unsigned long)regs->a1;
tlb_info.size = (unsigned long)regs->a2;
tlb_info.type = SBI_TLB_FLUSH_VMA;
tlb_info.size = (unsigned long)regs->a2;
tlb_info.type = SBI_TLB_FLUSH_VMA;
ret = sbi_ipi_send_many(scratch, (ulong *)regs->a0,
SBI_IPI_EVENT_SFENCE_VMA, &tlb_info);
break;
case SBI_ECALL_REMOTE_SFENCE_VMA_ASID:
tlb_info.start = (unsigned long)regs->a1;
tlb_info.size = (unsigned long)regs->a2;
tlb_info.asid = (unsigned long)regs->a3;
tlb_info.type = SBI_TLB_FLUSH_VMA_ASID;
tlb_info.size = (unsigned long)regs->a2;
tlb_info.asid = (unsigned long)regs->a3;
tlb_info.type = SBI_TLB_FLUSH_VMA_ASID;
ret = sbi_ipi_send_many(scratch, (ulong *)regs->a0,
SBI_IPI_EVENT_SFENCE_VMA_ASID, &tlb_info);
SBI_IPI_EVENT_SFENCE_VMA_ASID,
&tlb_info);
break;
case SBI_ECALL_SHUTDOWN:
sbi_system_shutdown(scratch, 0);
@@ -89,7 +89,7 @@ int sbi_ecall_handler(u32 hartid, ulong mcause,
break;
default:
regs->a0 = SBI_ENOTSUPP;
ret = 0;
ret = 0;
break;
};

20
lib/sbi_emulate_csr.c
View File

@@ -15,10 +15,8 @@
#include <sbi/sbi_error.h>
#include <sbi/sbi_timer.h>
int sbi_emulate_csr_read(int csr_num,
u32 hartid, ulong mstatus,
struct sbi_scratch *scratch,
ulong *csr_val)
int sbi_emulate_csr_read(int csr_num, u32 hartid, ulong mstatus,
struct sbi_scratch *scratch, ulong *csr_val)
{
ulong cen = -1UL;
@@ -85,18 +83,16 @@ int sbi_emulate_csr_read(int csr_num,
*csr_val = csr_read(CSR_MHPMEVENT4);
break;
default:
sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
__func__, hartid, csr_num);
sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n", __func__,
hartid, csr_num);
return SBI_ENOTSUPP;
};
return 0;
}
int sbi_emulate_csr_write(int csr_num,
u32 hartid, ulong mstatus,
struct sbi_scratch *scratch,
ulong csr_val)
int sbi_emulate_csr_write(int csr_num, u32 hartid, ulong mstatus,
struct sbi_scratch *scratch, ulong csr_val)
{
switch (csr_num) {
case CSR_CYCLE:
@@ -132,8 +128,8 @@ int sbi_emulate_csr_write(int csr_num,
csr_write(CSR_MHPMEVENT4, csr_val);
break;
default:
sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
__func__, hartid, csr_num);
sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n", __func__,
hartid, csr_num);
return SBI_ENOTSUPP;
};

20
lib/sbi_fifo.c
View File

@@ -12,12 +12,12 @@
#include <sbi/sbi_fifo.h>
#include <plat/string.h>
void sbi_fifo_init(struct sbi_fifo *fifo, void *queue_mem,
u16 entries, u16 entry_size)
void sbi_fifo_init(struct sbi_fifo *fifo, void *queue_mem, u16 entries,
u16 entry_size)
{
fifo->queue = queue_mem;
fifo->queue = queue_mem;
fifo->num_entries = entries;
fifo->entry_size = entry_size;
fifo->entry_size = entry_size;
SPIN_LOCK_INIT(&fifo->qlock);
fifo->avail = fifo->tail = 0;
memset(fifo->queue, 0, entries * entry_size);
@@ -75,7 +75,7 @@ bool sbi_fifo_is_empty(struct sbi_fifo *fifo)
static inline void __sbi_fifo_reset(struct sbi_fifo *fifo)
{
fifo->avail = 0;
fifo->tail = 0;
fifo->tail = 0;
memset(fifo->queue, 0, fifo->num_entries * fifo->entry_size);
}
@@ -99,13 +99,13 @@ bool sbi_fifo_reset(struct sbi_fifo *fifo)
* lead to deadlock.
*/
int sbi_fifo_inplace_update(struct sbi_fifo *fifo, void *in,
int (*fptr)(void *in, void *data))
int (*fptr)(void *in, void *data))
{
int i, index = 0;
int ret = SBI_FIFO_UNCHANGED;
void *entry;
if (!fifo || !in )
if (!fifo || !in)
return ret;
spin_lock(&fifo->qlock);
if (__sbi_fifo_is_empty(fifo)) {
@@ -113,12 +113,12 @@ int sbi_fifo_inplace_update(struct sbi_fifo *fifo, void *in,
return ret;
}
for (i = 0; i < fifo->avail; i ++) {
for (i = 0; i < fifo->avail; i++) {
index = fifo->tail + i;
if (index >= fifo->num_entries)
index = index - fifo->num_entries;
entry = (void *)fifo->queue + (u32) index * fifo->entry_size;
ret = fptr(in, entry);
entry = (void *)fifo->queue + (u32)index * fifo->entry_size;
ret = fptr(in, entry);
if (ret == SBI_FIFO_SKIP || ret == SBI_FIFO_UPDATED) {
break;
} else if (ret == SBI_FIFO_RESET) {

37
lib/sbi_hart.c
View File

@@ -35,8 +35,7 @@ static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
csr_write(CSR_MSTATUS, MSTATUS_FS);
/* Enable user/supervisor use of perf counters */
if (misa_extension('S') &&
sbi_platform_has_scounteren(plat))
if (misa_extension('S') && sbi_platform_has_scounteren(plat))
csr_write(CSR_SCOUNTEREN, -1);
if (sbi_platform_has_mcounteren(plat))
csr_write(CSR_MCOUNTEREN, -1);
@@ -88,8 +87,7 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
/* Send M-mode interrupts and most exceptions to S-mode */
interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
exceptions = (1U << CAUSE_MISALIGNED_FETCH) |
(1U << CAUSE_BREAKPOINT) |
exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
(1U << CAUSE_USER_ECALL);
if (sbi_platform_has_mfaults_delegation(plat))
exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
@@ -166,7 +164,7 @@ static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
return 0;
fw_size_log2 = log2roundup(scratch->fw_size);
fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
pmp_set(0, 0, fw_start, fw_size_log2);
@@ -175,8 +173,8 @@ static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
count = (PMP_COUNT - 1);
for (i = 0; i < count; i++) {
if (sbi_platform_pmp_region_info(plat, hartid, i,
&prot, &addr, &log2size))
if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
&log2size))
continue;
pmp_set(i + 1, prot, addr, log2size);
}
@@ -208,10 +206,9 @@ void __attribute__((noreturn)) sbi_hart_hang(void)
__builtin_unreachable();
}
void __attribute__((noreturn)) sbi_hart_switch_mode(unsigned long arg0,
unsigned long arg1,
unsigned long next_addr,
unsigned long next_mode)
void __attribute__((noreturn))
sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
unsigned long next_addr, unsigned long next_mode)
{
unsigned long val;
@@ -248,13 +245,13 @@ void __attribute__((noreturn)) sbi_hart_switch_mode(unsigned long arg0,
csr_write(CSR_UIE, 0);
}
register unsigned long a0 asm ("a0") = arg0;
register unsigned long a1 asm ("a1") = arg1;
__asm__ __volatile__ ("mret" : : "r" (a0), "r" (a1));
register unsigned long a0 asm("a0") = arg0;
register unsigned long a1 asm("a1") = arg1;
__asm__ __volatile__("mret" : : "r"(a0), "r"(a1));
__builtin_unreachable();
}
static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
static volatile unsigned long avail_hart_mask = 0;
void sbi_hart_mark_available(u32 hartid)
@@ -290,9 +287,9 @@ struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
return ((h2s)scratch->hartid_to_scratch)(hartid);
}
#define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
#define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
static spinlock_t coldboot_wait_bitmap_lock = SPIN_LOCK_INITIALIZER;
static unsigned long coldboot_wait_bitmap = 0;
static unsigned long coldboot_wait_bitmap = 0;
void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
{
@@ -302,7 +299,7 @@ void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
if ((sbi_platform_hart_count(plat) <= hartid) ||
(COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
sbi_hart_hang();
/* Set MSIE bit to receive IPI */
csr_set(CSR_MIE, MIP_MSIP);
@@ -325,9 +322,9 @@ void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
{
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
int max_hart = sbi_platform_hart_count(plat);
int max_hart = sbi_platform_hart_count(plat);
for(int i = 0; i < max_hart ; i++) {
for (int i = 0; i < max_hart; i++) {
/* send an IPI to every other hart */
spin_lock(&coldboot_wait_bitmap_lock);
if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))

40
lib/sbi_illegal_insn.c
View File

@@ -16,48 +16,45 @@
#include <sbi/sbi_illegal_insn.h>
#include <sbi/sbi_trap.h>
typedef int (*illegal_insn_func)(ulong insn,
u32 hartid, ulong mcause,
typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause,
struct sbi_trap_regs *regs,
struct sbi_scratch *scratch);
static int truly_illegal_insn(ulong insn,
u32 hartid, ulong mcause,
static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause,
struct sbi_trap_regs *regs,
struct sbi_scratch *scratch)
{
return sbi_trap_redirect(regs, scratch, regs->mepc, mcause, insn);
}
static int system_opcode_insn(ulong insn,
u32 hartid, ulong mcause,
static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause,
struct sbi_trap_regs *regs,
struct sbi_scratch *scratch)
{
int do_write, rs1_num = (insn >> 15) & 0x1f;
ulong rs1_val = GET_RS1(insn, regs);
int csr_num = (u32)insn >> 20;
int csr_num = (u32)insn >> 20;
ulong csr_val, new_csr_val;
if (sbi_emulate_csr_read(csr_num, hartid, regs->mstatus,
scratch, &csr_val))
return truly_illegal_insn(insn, hartid, mcause,
regs, scratch);
if (sbi_emulate_csr_read(csr_num, hartid, regs->mstatus, scratch,
&csr_val))
return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
do_write = rs1_num;
switch (GET_RM(insn)) {
case 1:
new_csr_val = rs1_val;
do_write = 1;
do_write = 1;
break;
case 2:
new_csr_val = csr_val | rs1_val;
break;
case 3: new_csr_val = csr_val & ~rs1_val;
case 3:
new_csr_val = csr_val & ~rs1_val;
break;
case 5:
new_csr_val = rs1_num;
do_write = 1;
do_write = 1;
break;
case 6:
new_csr_val = csr_val | rs1_num;
@@ -66,15 +63,12 @@ static int system_opcode_insn(ulong insn,
new_csr_val = csr_val & ~rs1_num;
break;
default:
return truly_illegal_insn(insn, hartid, mcause,
regs, scratch);
return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
};
if (do_write &&
sbi_emulate_csr_write(csr_num, hartid, regs->mstatus,
scratch, new_csr_val))
return truly_illegal_insn(insn, hartid, mcause,
regs, scratch);
if (do_write && sbi_emulate_csr_write(csr_num, hartid, regs->mstatus,
scratch, new_csr_val))
return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
SET_RD(insn, regs, csr_val);
@@ -128,8 +122,8 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
if (insn == 0)
insn = get_insn(regs->mepc, NULL);
if ((insn & 3) != 3)
return truly_illegal_insn(insn, hartid, mcause,
regs, scratch);
return truly_illegal_insn(insn, hartid, mcause, regs,
scratch);
}
return illegal_insn_table[(insn & 0x7c) >> 2](insn, hartid, mcause,

29
lib/sbi_init.c
View File

@@ -18,14 +18,14 @@
#include <sbi/sbi_timer.h>
#include <sbi/sbi_version.h>
#define BANNER \
" ____ _____ ____ _____\n" \
" / __ \\ / ____| _ \\_ _|\n" \
" | | | |_ __ ___ _ __ | (___ | |_) || |\n" \
#define BANNER \
" ____ _____ ____ _____\n" \
" / __ \\ / ____| _ \\_ _|\n" \
" | | | |_ __ ___ _ __ | (___ | |_) || |\n" \
" | | | | '_ \\ / _ \\ '_ \\ \\___ \\| _ < | |\n" \
" | |__| | |_) | __/ | | |____) | |_) || |_\n" \
" \\____/| .__/ \\___|_| |_|_____/|____/_____|\n" \
" | |\n" \
" | |__| | |_) | __/ | | |____) | |_) || |_\n" \
" \\____/| .__/ \\___|_| |_|_____/|____/_____|\n" \
" | |\n" \
" |_|\n\n"
static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
@@ -34,9 +34,8 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
misa_string(str, sizeof(str));
sbi_printf("\nOpenSBI v%d.%d (%s %s)\n",
OPENSBI_VERSION_MAJOR, OPENSBI_VERSION_MINOR,
__DATE__, __TIME__);
sbi_printf("\nOpenSBI v%d.%d (%s %s)\n", OPENSBI_VERSION_MAJOR,
OPENSBI_VERSION_MINOR, __DATE__, __TIME__);
sbi_printf(BANNER);
@@ -97,8 +96,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
if (!sbi_platform_has_hart_hotplug(plat))
sbi_hart_wake_coldboot_harts(scratch, hartid);
sbi_hart_mark_available(hartid);
sbi_hart_switch_mode(hartid, scratch->next_arg1,
scratch->next_addr, scratch->next_mode);
sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
scratch->next_mode);
}
static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
@@ -162,13 +161,13 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
*/
void __noreturn sbi_init(struct sbi_scratch *scratch)
{
bool coldboot = FALSE;
u32 hartid = sbi_current_hartid();
bool coldboot = FALSE;
u32 hartid = sbi_current_hartid();
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
if (sbi_platform_hart_disabled(plat, hartid))
sbi_hart_hang();
if (atomic_add_return(&coldboot_lottery, 1) == 1)
coldboot = TRUE;

67
lib/sbi_ipi.c
View File

@@ -34,10 +34,9 @@ static inline int __sbi_tlb_fifo_range_check(struct sbi_tlb_info *curr,
curr_end = curr->start + curr->size;
if (next->start <= curr->start && next_end > curr_end) {
curr->start = next->start;
curr->size = next->size;
ret = SBI_FIFO_UPDATED;
} else if (next->start >= curr->start &&
next_end <= curr_end) {
curr->size = next->size;
ret = SBI_FIFO_UPDATED;
} else if (next->start >= curr->start && next_end <= curr_end) {
ret = SBI_FIFO_SKIP;
}
@@ -69,8 +68,8 @@ int sbi_tlb_fifo_update_cb(void *in, void *data)
if (!in && !!data)
return ret;
curr = (struct sbi_tlb_info *) data;
next = (struct sbi_tlb_info *) in;
curr = (struct sbi_tlb_info *)data;
next = (struct sbi_tlb_info *)in;
if (next->type == SBI_TLB_FLUSH_VMA_ASID &&
curr->type == SBI_TLB_FLUSH_VMA_ASID) {
if (next->asid == curr->asid)
@@ -86,11 +85,11 @@ int sbi_tlb_fifo_update_cb(void *in, void *data)
return ret;
}
static int sbi_ipi_send(struct sbi_scratch *scratch, u32 hartid,
u32 event, void *data)
static int sbi_ipi_send(struct sbi_scratch *scratch, u32 hartid, u32 event,
void *data)
{
struct sbi_scratch *remote_scratch = NULL;
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
struct sbi_fifo *ipi_tlb_fifo;
int ret = SBI_FIFO_UNCHANGED;
@@ -104,12 +103,12 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 hartid,
if (event == SBI_IPI_EVENT_SFENCE_VMA ||
event == SBI_IPI_EVENT_SFENCE_VMA_ASID) {
ipi_tlb_fifo = sbi_tlb_fifo_head_ptr(remote_scratch);
ret = sbi_fifo_inplace_update(ipi_tlb_fifo, data,
sbi_tlb_fifo_update_cb);
ret = sbi_fifo_inplace_update(ipi_tlb_fifo, data,
sbi_tlb_fifo_update_cb);
if (ret == SBI_FIFO_SKIP || ret == SBI_FIFO_UPDATED) {
goto done;
}
while(sbi_fifo_enqueue(ipi_tlb_fifo, data) < 0) {
while (sbi_fifo_enqueue(ipi_tlb_fifo, data) < 0) {
/**
* For now, Busy loop until there is space in the fifo.
* There may be case where target hart is also
@@ -132,8 +131,8 @@ done:
return 0;
}
int sbi_ipi_send_many(struct sbi_scratch *scratch,
ulong *pmask, u32 event, void *data)
int sbi_ipi_send_many(struct sbi_scratch *scratch, ulong *pmask, u32 event,
void *data)
{
ulong i, m;
ulong mask = sbi_hart_available_mask();
@@ -153,7 +152,6 @@ int sbi_ipi_send_many(struct sbi_scratch *scratch,
if (mask & (1UL << hartid))
sbi_ipi_send(scratch, hartid, event, data);
return 0;
}
@@ -170,7 +168,7 @@ static void sbi_ipi_tlb_flush_all()
static void sbi_ipi_sfence_vma(struct sbi_tlb_info *tinfo)
{
unsigned long start = tinfo->start;
unsigned long size = tinfo->size;
unsigned long size = tinfo->size;
unsigned long i;
if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
@@ -179,17 +177,18 @@ static void sbi_ipi_sfence_vma(struct sbi_tlb_info *tinfo)
}
for (i = 0; i < size; i += PAGE_SIZE) {
__asm__ __volatile__ ("sfence.vma %0"
: : "r" (start + i)
: "memory");
__asm__ __volatile__("sfence.vma %0"
:
: "r"(start + i)
: "memory");
}
}
static void sbi_ipi_sfence_vma_asid(struct sbi_tlb_info *tinfo)
{
unsigned long start = tinfo->start;
unsigned long size = tinfo->size;
unsigned long asid = tinfo->asid;
unsigned long size = tinfo->size;
unsigned long asid = tinfo->asid;
unsigned long i;
if (start == 0 && size == 0) {
@@ -199,16 +198,18 @@ static void sbi_ipi_sfence_vma_asid(struct sbi_tlb_info *tinfo)
/* Flush entire MM context for a given ASID */
if (size == SBI_TLB_FLUSH_ALL) {
__asm__ __volatile__ ("sfence.vma x0, %0"
: : "r" (asid)
: "memory");
__asm__ __volatile__("sfence.vma x0, %0"
:
: "r"(asid)
: "memory");
return;
}
for (i = 0; i < size; i += PAGE_SIZE) {
__asm__ __volatile__ ("sfence.vma %0, %1"
: : "r" (start + i), "r" (asid)
: "memory");
__asm__ __volatile__("sfence.vma %0, %1"
:
: "r"(start + i), "r"(asid)
: "memory");
}
}
@@ -218,7 +219,7 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
struct sbi_tlb_info tinfo;
unsigned int ipi_event;
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
struct sbi_fifo *ipi_tlb_fifo = sbi_tlb_fifo_head_ptr(scratch);
struct sbi_fifo *ipi_tlb_fifo = sbi_tlb_fifo_head_ptr(scratch);
u32 hartid = sbi_current_hartid();
sbi_platform_ipi_clear(plat, hartid);
@@ -236,7 +237,7 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
break;
case SBI_IPI_EVENT_SFENCE_VMA:
case SBI_IPI_EVENT_SFENCE_VMA_ASID:
while(!sbi_fifo_dequeue(ipi_tlb_fifo, &tinfo)) {
while (!sbi_fifo_dequeue(ipi_tlb_fifo, &tinfo)) {
if (tinfo.type == SBI_TLB_FLUSH_VMA)
sbi_ipi_sfence_vma(&tinfo);
else if (tinfo.type == SBI_TLB_FLUSH_VMA_ASID)
@@ -248,8 +249,9 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
sbi_hart_hang();
break;
};
ipi_type = atomic_raw_clear_bit(ipi_event, &sbi_ipi_data_ptr(scratch)->ipi_type);
} while(ipi_type > 0);
ipi_type = atomic_raw_clear_bit(
ipi_event, &sbi_ipi_data_ptr(scratch)->ipi_type);
} while (ipi_type > 0);
}
int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
@@ -263,6 +265,5 @@ int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
/* Enable software interrupts */
csr_set(CSR_MIE, MIP_MSIP);
return sbi_platform_ipi_init(sbi_platform_ptr(scratch),
cold_boot);
return sbi_platform_ipi_init(sbi_platform_ptr(scratch), cold_boot);
}

72
lib/sbi_misaligned_ldst.c
View File

@@ -31,61 +31,61 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
int i, fp = 0, shift = 0, len = 0;
if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
len = 4;
len = 4;
shift = 8 * (sizeof(ulong) - len);
#if __riscv_xlen == 64
} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
len = 8;
len = 8;
shift = 8 * (sizeof(ulong) - len);
} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
len = 4;
#endif
} else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
fp = 1;
fp = 1;
len = 8;
} else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
fp = 1;
fp = 1;
len = 4;
} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
len = 2;
len = 2;
shift = 8 * (sizeof(ulong) - len);
} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
len = 2;
#ifdef __riscv_compressed
# if __riscv_xlen >= 64
#if __riscv_xlen >= 64
} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
len = 8;
len = 8;
shift = 8 * (sizeof(ulong) - len);
insn = RVC_RS2S(insn) << SH_RD;
insn = RVC_RS2S(insn) << SH_RD;
} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
((insn >> SH_RD) & 0x1f)) {
len = 8;
len = 8;
shift = 8 * (sizeof(ulong) - len);
# endif
} else if ((insn & INSN_MASK_C_LW) ==INSN_MATCH_C_LW) {
len = 4;
#endif
} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
len = 4;
shift = 8 * (sizeof(ulong) - len);
insn = RVC_RS2S(insn) << SH_RD;
insn = RVC_RS2S(insn) << SH_RD;
} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
((insn >> SH_RD) & 0x1f)) {
len = 4;
len = 4;
shift = 8 * (sizeof(ulong) - len);
} else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
fp = 1;
len = 8;
fp = 1;
len = 8;
insn = RVC_RS2S(insn) << SH_RD;
} else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
fp = 1;
fp = 1;
len = 8;
# if __riscv_xlen == 32
#if __riscv_xlen == 32
} else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
fp = 1;
len = 4;
fp = 1;
len = 4;
insn = RVC_RS2S(insn) << SH_RD;
} else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
fp = 1;
fp = 1;
len = 4;
# endif
#endif
#endif
} else
return SBI_EILL;
@@ -124,44 +124,44 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
len = 8;
#endif
} else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) {
len = 8;
len = 8;
val.data_u64 = GET_F64_RS2(insn, regs);
} else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) {
len = 4;
len = 4;
val.data_ulong = GET_F32_RS2(insn, regs);
} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
len = 2;
#ifdef __riscv_compressed
# if __riscv_xlen >= 64
#if __riscv_xlen >= 64
} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
len = 8;
len = 8;
val.data_ulong = GET_RS2S(insn, regs);
} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
((insn >> SH_RD) & 0x1f)) {
len = 8;
len = 8;
val.data_ulong = GET_RS2C(insn, regs);
# endif
#endif
} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
len = 4;
len = 4;
val.data_ulong = GET_RS2S(insn, regs);
} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
((insn >> SH_RD) & 0x1f)) {
len = 4;
len = 4;
val.data_ulong = GET_RS2C(insn, regs);
} else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {
len = 8;
len = 8;
val.data_u64 = GET_F64_RS2S(insn, regs);
} else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {
len = 8;
len = 8;
val.data_u64 = GET_F64_RS2C(insn, regs);
# if __riscv_xlen == 32
#if __riscv_xlen == 32
} else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {
len = 4;
len = 4;
val.data_ulong = GET_F32_RS2S(insn, regs);
} else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {
len = 4;
len = 4;
val.data_ulong = GET_F32_RS2C(insn, regs);
# endif
#endif
#endif
} else
return SBI_EILL;

14
lib/sbi_system.c
View File

@@ -15,26 +15,24 @@
int sbi_system_early_init(struct sbi_scratch *scratch, bool cold_boot)
{
return sbi_platform_early_init(sbi_platform_ptr(scratch),
cold_boot);
return sbi_platform_early_init(sbi_platform_ptr(scratch), cold_boot);
}
int sbi_system_final_init(struct sbi_scratch *scratch, bool cold_boot)
{
return sbi_platform_final_init(sbi_platform_ptr(scratch),
cold_boot);
return sbi_platform_final_init(sbi_platform_ptr(scratch), cold_boot);
}
void __attribute__((noreturn)) sbi_system_reboot(struct sbi_scratch *scratch,
u32 type)
void __attribute__((noreturn))
sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
{
sbi_platform_system_reboot(sbi_platform_ptr(scratch), type);
sbi_hart_hang();
}
void __attribute__((noreturn)) sbi_system_shutdown(struct sbi_scratch *scratch,
u32 type)
void __attribute__((noreturn))
sbi_system_shutdown(struct sbi_scratch *scratch, u32 type)
{
/* First try the platform-specific method */
sbi_platform_system_shutdown(sbi_platform_ptr(scratch), type);

23
lib/sbi_timer.c
View File

@@ -16,13 +16,12 @@
u64 get_ticks(void)
{
u32 lo, hi, tmp;
__asm__ __volatile__ (
"1:\n"
"rdtimeh %0\n"
"rdtime %1\n"
"rdtimeh %2\n"
"bne %0, %2, 1b"
: "=&r" (hi), "=&r" (lo), "=&r" (tmp));
__asm__ __volatile__("1:\n"
"rdtimeh %0\n"
"rdtime %1\n"
"rdtimeh %2\n"
"bne %0, %2, 1b"
: "=&r"(hi), "=&r"(lo), "=&r"(tmp));
return ((u64)hi << 32) | lo;
}
#else
@@ -30,9 +29,7 @@ u64 get_ticks(void)
{
unsigned long n;
__asm__ __volatile__ (
"rdtime %0"
: "=r" (n));
__asm__ __volatile__("rdtime %0" : "=r"(n));
return n;
}
#endif
@@ -54,8 +51,7 @@ void sbi_timer_event_stop(struct sbi_scratch *scratch)
void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event)
{
sbi_platform_timer_event_start(sbi_platform_ptr(scratch),
next_event);
sbi_platform_timer_event_start(sbi_platform_ptr(scratch), next_event);
csr_clear(CSR_MIP, MIP_STIP);
csr_set(CSR_MIE, MIP_MTIP);
}
@@ -68,6 +64,5 @@ void sbi_timer_process(struct sbi_scratch *scratch)
int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
{
return sbi_platform_timer_init(sbi_platform_ptr(scratch),
cold_boot);
return sbi_platform_timer_init(sbi_platform_ptr(scratch), cold_boot);
}

96
lib/sbi_trap.c
View File

@@ -19,49 +19,47 @@
#include <sbi/sbi_timer.h>
#include <sbi/sbi_trap.h>
static void __noreturn sbi_trap_error(const char *msg,
int rc, u32 hartid,
static void __noreturn sbi_trap_error(const char *msg, int rc, u32 hartid,
ulong mcause, ulong mtval,
struct sbi_trap_regs *regs)
{
sbi_printf("%s: hart%d: %s (error %d)\n",
__func__, hartid, msg, rc);
sbi_printf("%s: hart%d: mcause=0x%"PRILX" mtval=0x%"PRILX"\n",
sbi_printf("%s: hart%d: %s (error %d)\n", __func__, hartid, msg, rc);
sbi_printf("%s: hart%d: mcause=0x%" PRILX " mtval=0x%" PRILX "\n",
__func__, hartid, mcause, mtval);
sbi_printf("%s: hart%d: mepc=0x%"PRILX" mstatus=0x%"PRILX"\n",
sbi_printf("%s: hart%d: mepc=0x%" PRILX " mstatus=0x%" PRILX "\n",
__func__, hartid, regs->mepc, regs->mstatus);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "ra", regs->ra, "sp", regs->sp);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "gp", regs->gp, "tp", regs->tp);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s0", regs->s0, "s1", regs->s1);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "a0", regs->a0, "a1", regs->a1);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "a2", regs->a2, "a3", regs->a3);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "a4", regs->a4, "a5", regs->a5);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "a6", regs->a6, "a7", regs->a7);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s2", regs->s2, "s3", regs->s3);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s4", regs->s4, "s5", regs->s5);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s6", regs->s6, "s7", regs->s7);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s8", regs->s8, "s9", regs->s9);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "s10", regs->s10, "s11", regs->s11);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "t0", regs->t0, "t1", regs->t1);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "t2", regs->t2, "t3", regs->t3);
sbi_printf("%s: hart%d: %s=0x%"PRILX" %s=0x%"PRILX"\n",
__func__, hartid, "t4", regs->t4, "t5", regs->t5);
sbi_printf("%s: hart%d: %s=0x%"PRILX"\n",
__func__, hartid, "t6", regs->t6);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "ra", regs->ra, "sp", regs->sp);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "gp", regs->gp, "tp", regs->tp);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s0", regs->s0, "s1", regs->s1);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "a0", regs->a0, "a1", regs->a1);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "a2", regs->a2, "a3", regs->a3);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "a4", regs->a4, "a5", regs->a5);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "a6", regs->a6, "a7", regs->a7);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s2", regs->s2, "s3", regs->s3);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s4", regs->s4, "s5", regs->s5);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s6", regs->s6, "s7", regs->s7);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s8", regs->s8, "s9", regs->s9);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "s10", regs->s10, "s11", regs->s11);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "t0", regs->t0, "t1", regs->t1);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "t2", regs->t2, "t3", regs->t3);
sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
hartid, "t4", regs->t4, "t5", regs->t5);
sbi_printf("%s: hart%d: %s=0x%" PRILX "\n", __func__, hartid, "t6",
regs->t6);
sbi_hart_hang();
}
@@ -77,8 +75,7 @@ static void __noreturn sbi_trap_error(const char *msg,
*
* @return 0 on success and negative error code on failure
*/
int sbi_trap_redirect(struct sbi_trap_regs *regs,
struct sbi_scratch *scratch,
int sbi_trap_redirect(struct sbi_trap_regs *regs, struct sbi_scratch *scratch,
ulong epc, ulong cause, ulong tval)
{
ulong new_mstatus, prev_mode;
@@ -100,8 +97,8 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
new_mstatus = regs->mstatus;
/* Clear MPP, SPP, SPIE, and SIE */
new_mstatus &= ~(MSTATUS_MPP |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE);
new_mstatus &=
~(MSTATUS_MPP | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE);
/* Set SPP */
if (prev_mode == PRV_S)
@@ -135,10 +132,9 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
* @param regs pointer to register state
* @param scratch pointer to sbi_scratch of current HART
*/
void sbi_trap_handler(struct sbi_trap_regs *regs,
struct sbi_scratch *scratch)
void sbi_trap_handler(struct sbi_trap_regs *regs, struct sbi_scratch *scratch)
{
int rc = SBI_ENOTSUPP;
int rc = SBI_ENOTSUPP;
const char *msg = "trap handler failed";
u32 hartid = sbi_current_hartid();
ulong mcause = csr_read(CSR_MCAUSE);
@@ -162,7 +158,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
switch (mcause) {
case CAUSE_ILLEGAL_INSTRUCTION:
rc = sbi_illegal_insn_handler(hartid, mcause, regs, scratch);
rc = sbi_illegal_insn_handler(hartid, mcause, regs, scratch);
msg = "illegal instruction handler failed";
break;
case CAUSE_MISALIGNED_LOAD:
@@ -170,12 +166,13 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
msg = "misaligned load handler failed";
break;
case CAUSE_MISALIGNED_STORE:
rc = sbi_misaligned_store_handler(hartid, mcause, regs, scratch);
rc = sbi_misaligned_store_handler(hartid, mcause, regs,
scratch);
msg = "misaligned store handler failed";
break;
case CAUSE_SUPERVISOR_ECALL:
case CAUSE_HYPERVISOR_ECALL:
rc = sbi_ecall_handler(hartid, mcause, regs, scratch);
rc = sbi_ecall_handler(hartid, mcause, regs, scratch);
msg = "ecall handler failed";
break;
default:
@@ -186,6 +183,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
trap_error:
if (rc) {
sbi_trap_error(msg, rc, hartid, mcause, csr_read(CSR_MTVAL), regs);
sbi_trap_error(msg, rc, hartid, mcause, csr_read(CSR_MTVAL),
regs);
}
}