forked from Mirrors/opensbi
all: run clang-format and update checked-in files
Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:

committed by
Anup Patel

parent
fbf986ac2a
commit
10baa64c02
@@ -21,28 +21,49 @@
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#ifdef __riscv_flen
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#define GET_F32_REG(insn, pos, regs) ({ \
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register s32 value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm ("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(value) :: "t0"); \
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value; })
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#define SET_F32_REG(insn, pos, regs, val) ({ \
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register u32 value asm("a0") = (val); \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile ("1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); })
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#define GET_F32_REG(insn, pos, regs) \
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({ \
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register s32 value asm("a0") = \
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SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp), "+&r"(value)::"t0"); \
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value; \
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})
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#define SET_F32_REG(insn, pos, regs, val) \
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({ \
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register u32 value asm("a0") = (val); \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile( \
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"1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp) \
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: "r"(value), "r"(offset) \
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: "t0"); \
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})
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#define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0)
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#define GET_F64_REG(insn, pos, regs) ({ \
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register ulong value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm ("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(value) :: "t0"); \
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sizeof(ulong) == 4 ? *(int64_t*)value : (int64_t)value; })
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#define SET_F64_REG(insn, pos, regs, val) ({ \
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uint64_t __val = (val); \
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register ulong value asm("a0") = sizeof(ulong) == 4 ? (ulong)&__val : (ulong)__val; \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); })
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#define GET_F64_REG(insn, pos, regs) \
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({ \
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register ulong value asm("a0") = \
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SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp), "+&r"(value)::"t0"); \
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sizeof(ulong) == 4 ? *(int64_t *)value : (int64_t)value; \
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})
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#define SET_F64_REG(insn, pos, regs, val) \
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({ \
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uint64_t __val = (val); \
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register ulong value asm("a0") = \
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sizeof(ulong) == 4 ? (ulong)&__val : (ulong)__val; \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile( \
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"1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp) \
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: "r"(value), "r"(offset) \
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: "t0"); \
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})
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#define GET_FCSR() csr_read(CSR_FCSR)
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#define SET_FCSR(value) csr_write(CSR_FCSR, (value))
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#define GET_FRM() csr_read(CSR_FRM)
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@@ -50,7 +71,7 @@
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#define GET_FFLAGS() csr_read(CSR_FFLAGS)
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#define SET_FFLAGS(value) csr_write(CSR_FFLAGS, (value))
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#define SET_FS_DIRTY() ((void) 0)
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#define SET_FS_DIRTY() ((void)0)
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#else
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#error "Floating point emulation not supported.\n"
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@@ -62,8 +83,10 @@
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#define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs))
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#define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs))
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#define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs))
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#define SET_F32_RD(insn, regs, val) (SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define SET_F64_RD(insn, regs, val) (SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define SET_F32_RD(insn, regs, val) \
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(SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define SET_F64_RD(insn, regs, val) \
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(SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs))
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#define GET_F32_RS2S(insn, regs) (GET_F32_REG(RVC_RS2S(insn), 0, regs))
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