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lib: Do not access mi/edeleg register if S mode is not present.

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As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.

We shouldn't access these CSRs if non S-mode harts.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra
2019-01-21 18:17:45 -08:00
committed by Anup Patel
parent bc545539d2
commit 023aa6bb04
1 changed files with 13 additions and 15 deletions
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10
lib/sbi_hart.c
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@@ -82,11 +82,10 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
struct sbi_platform *plat = sbi_platform_ptr(scratch); struct sbi_platform *plat = sbi_platform_ptr(scratch);
unsigned long interrupts, exceptions; unsigned long interrupts, exceptions;
if (!misa_extension('S')) { if (!misa_extension('S'))
/* No delegation possible */ /* No delegation possible as mideleg does not exist*/
interrupts = 0; return 0;
exceptions = 0;
} else {
/* Send M-mode interrupts and most exceptions to S-mode */ /* Send M-mode interrupts and most exceptions to S-mode */
interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
exceptions = (1U << CAUSE_MISALIGNED_FETCH) | exceptions = (1U << CAUSE_MISALIGNED_FETCH) |
@@ -96,7 +95,6 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) | exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
(1U << CAUSE_LOAD_PAGE_FAULT) | (1U << CAUSE_LOAD_PAGE_FAULT) |
(1U << CAUSE_STORE_PAGE_FAULT); (1U << CAUSE_STORE_PAGE_FAULT);
}
csr_write(mideleg, interrupts); csr_write(mideleg, interrupts);
csr_write(medeleg, exceptions); csr_write(medeleg, exceptions);