198 lines
4.9 KiB
ArmAsm
198 lines
4.9 KiB
ArmAsm
/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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.extern pxCurrentTCB
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.extern vTaskISRHandler
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.extern vTaskSwitchContext
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.extern uxCriticalNesting
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.extern pulISRStack
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.global __FreeRTOS_interrupt_handler
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.global VPortYieldASM
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.global vStartFirstTask
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.macro portSAVE_CONTEXT
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/* Make room for the context on the stack. */
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addik r1, r1, -132
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/* Save r31 so it can then be used. */
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swi r31, r1, 4
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/* Copy the msr into r31 - this is stacked later. */
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mfs r31, rmsr
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/* Stack general registers. */
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swi r30, r1, 12
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swi r29, r1, 16
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swi r28, r1, 20
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swi r27, r1, 24
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swi r26, r1, 28
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swi r25, r1, 32
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swi r24, r1, 36
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swi r23, r1, 40
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swi r22, r1, 44
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swi r21, r1, 48
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swi r20, r1, 52
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swi r19, r1, 56
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swi r18, r1, 60
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swi r17, r1, 64
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swi r16, r1, 68
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swi r15, r1, 72
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swi r13, r1, 80
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swi r12, r1, 84
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swi r11, r1, 88
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swi r10, r1, 92
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swi r9, r1, 96
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swi r8, r1, 100
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swi r7, r1, 104
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swi r6, r1, 108
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swi r5, r1, 112
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swi r4, r1, 116
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swi r3, r1, 120
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swi r2, r1, 124
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/* Stack the critical section nesting value. */
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lwi r3, r0, uxCriticalNesting
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swi r3, r1, 128
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/* Save the top of stack value to the TCB. */
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lwi r3, r0, pxCurrentTCB
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sw r1, r0, r3
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.endm
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.macro portRESTORE_CONTEXT
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/* Load the top of stack value from the TCB. */
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lwi r3, r0, pxCurrentTCB
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lw r1, r0, r3
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/* Restore the general registers. */
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lwi r31, r1, 4
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lwi r30, r1, 12
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lwi r29, r1, 16
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lwi r28, r1, 20
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lwi r27, r1, 24
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lwi r26, r1, 28
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lwi r25, r1, 32
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lwi r24, r1, 36
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lwi r23, r1, 40
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lwi r22, r1, 44
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lwi r21, r1, 48
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lwi r20, r1, 52
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lwi r19, r1, 56
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lwi r18, r1, 60
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lwi r17, r1, 64
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lwi r16, r1, 68
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lwi r15, r1, 72
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lwi r14, r1, 76
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lwi r13, r1, 80
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lwi r12, r1, 84
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lwi r11, r1, 88
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lwi r10, r1, 92
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lwi r9, r1, 96
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lwi r8, r1, 100
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lwi r7, r1, 104
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lwi r6, r1, 108
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lwi r5, r1, 112
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lwi r4, r1, 116
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lwi r2, r1, 124
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/* Load the critical nesting value. */
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lwi r3, r1, 128
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swi r3, r0, uxCriticalNesting
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/* Obtain the MSR value from the stack. */
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lwi r3, r1, 8
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/* Are interrupts enabled in the MSR? If so return using an return from
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interrupt instruction to ensure interrupts are enabled only once the task
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is running again. */
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andi r3, r3, 2
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beqid r3, 36
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or r0, r0, r0
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/* Reload the rmsr from the stack, clear the enable interrupt bit in the
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value before saving back to rmsr register, then return enabling interrupts
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as we return. */
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lwi r3, r1, 8
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andi r3, r3, ~2
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mts rmsr, r3
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lwi r3, r1, 120
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addik r1, r1, 132
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rtid r14, 0
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or r0, r0, r0
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/* Reload the rmsr from the stack, place it in the rmsr register, and
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return without enabling interrupts. */
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lwi r3, r1, 8
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mts rmsr, r3
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lwi r3, r1, 120
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addik r1, r1, 132
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rtsd r14, 0
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or r0, r0, r0
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.endm
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.text
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.align 2
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__FreeRTOS_interrupt_handler:
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portSAVE_CONTEXT
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/* Entered via an interrupt so interrupts must be enabled in msr. */
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ori r31, r31, 2
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/* Stack msr. */
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swi r31, r1, 8
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/* Stack the return address. As we entered via an interrupt we do
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not need to modify the return address prior to stacking. */
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swi r14, r1, 76
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/* Now switch to use the ISR stack. */
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lwi r3, r0, pulISRStack
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add r1, r3, r0
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bralid r15, vTaskISRHandler
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or r0, r0, r0
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portRESTORE_CONTEXT
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VPortYieldASM:
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portSAVE_CONTEXT
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/* Stack msr. */
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swi r31, r1, 8
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/* Modify the return address so we return to the instruction after the
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exception. */
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addi r14, r14, 8
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swi r14, r1, 76
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/* Now switch to use the ISR stack. */
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lwi r3, r0, pulISRStack
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add r1, r3, r0
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bralid r15, vTaskSwitchContext
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or r0, r0, r0
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portRESTORE_CONTEXT
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vStartFirstTask:
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portRESTORE_CONTEXT
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