664 lines
20 KiB
C
664 lines
20 KiB
C
/*
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FreeRTOS+TCP V2.0.11
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Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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the Software, and to permit persons to whom the Software is furnished to do so,
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subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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http://aws.amazon.com/freertos
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http://www.FreeRTOS.org
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*/
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#include "FreeRTOS.h"
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#include "task.h"
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#include "timers.h"
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#include "semphr.h"
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/* FreeRTOS+TCP includes. */
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#include "FreeRTOS_IP.h"
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#include "FreeRTOS_Sockets.h"
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#include "FreeRTOS_IP_Private.h"
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#include "NetworkBufferManagement.h"
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#include "Zynq/x_emacpsif.h"
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#include "Zynq/x_topology.h"
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#include "xstatus.h"
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#include "xparameters.h"
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#include "xparameters_ps.h"
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#include "xil_exception.h"
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#include "xil_mmu.h"
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#include "uncached_memory.h"
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/* Two defines used to set or clear the EMAC interrupt */
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#define INTC_BASE_ADDR XPAR_SCUGIC_CPU_BASEADDR
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#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR
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#if( ipconfigPACKET_FILLER_SIZE != 2 )
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#error Please define ipconfigPACKET_FILLER_SIZE as the value '2'
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#endif
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#define TX_OFFSET ipconfigPACKET_FILLER_SIZE
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/* Defined in NetworkInterface.c */
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extern TaskHandle_t xEMACTaskHandle;
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/*
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pxDMA_tx_buffers: these are character arrays, each one is big enough to hold 1 MTU.
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The actual TX buffers are located in uncached RAM.
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*/
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static unsigned char *pxDMA_tx_buffers[ ipconfigNIC_N_TX_DESC ] = { NULL };
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/*
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pxDMA_rx_buffers: these are pointers to 'NetworkBufferDescriptor_t'.
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Once a message has been received by the EMAC, the descriptor can be passed
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immediately to the IP-task.
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*/
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static NetworkBufferDescriptor_t *pxDMA_rx_buffers[ ipconfigNIC_N_RX_DESC ] = { NULL };
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/*
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The FreeRTOS+TCP port is using a fixed 'topology', which is declared in
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./portable/NetworkInterface/Zynq/NetworkInterface.c
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*/
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extern struct xtopology_t xXTopology;
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static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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/*
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The FreeRTOS+TCP port does not make use of "src/xemacps_bdring.c".
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In stead 'struct xemacpsif_s' has a "head" and a "tail" index.
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"head" is the next index to be written, used.
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"tail" is the next index to be read, freed.
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*/
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int is_tx_space_available( xemacpsif_s *xemacpsif )
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{
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size_t uxCount;
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if( xTXDescriptorSemaphore != NULL )
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{
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uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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}
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else
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{
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uxCount = ( UBaseType_t ) 0u;
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}
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return uxCount;
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}
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void emacps_check_tx( xemacpsif_s *xemacpsif )
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{
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int tail = xemacpsif->txTail;
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int head = xemacpsif->txHead;
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size_t uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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/* uxCount is the number of TX descriptors that are in use by the DMA. */
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/* When done, "TXBUF_USED" will be set. */
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while( ( uxCount > 0 ) && ( ( xemacpsif->txSegments[ tail ].flags & XEMACPS_TXBUF_USED_MASK ) != 0 ) )
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{
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if( ( tail == head ) && ( uxCount != ipconfigNIC_N_TX_DESC ) )
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{
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break;
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}
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#if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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#warning ipconfigZERO_COPY_TX_DRIVER is defined
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{
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void *pvBuffer = pxDMA_tx_buffers[ tail ];
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NetworkBufferDescriptor_t *pxBuffer;
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if( pvBuffer != NULL )
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{
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pxDMA_tx_buffers[ tail ] = NULL;
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pxBuffer = pxPacketBuffer_to_NetworkBuffer( pvBuffer );
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if( pxBuffer != NULL )
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{
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vReleaseNetworkBufferAndDescriptor( pxBuffer );
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}
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else
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{
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FreeRTOS_printf( ( "emacps_check_tx: Can not find network buffer\n" ) );
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}
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}
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}
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#endif
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/* Clear all but the "used" and "wrap" bits. */
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if( tail < ipconfigNIC_N_TX_DESC - 1 )
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{
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xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK;
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}
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else
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{
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xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK;
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}
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uxCount--;
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/* Tell the counting semaphore that one more TX descriptor is available. */
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xSemaphoreGive( xTXDescriptorSemaphore );
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if( ++tail == ipconfigNIC_N_TX_DESC )
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{
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tail = 0;
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}
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xemacpsif->txTail = tail;
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}
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return;
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}
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void emacps_send_handler(void *arg)
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{
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xemacpsif_s *xemacpsif;
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BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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xemacpsif = (xemacpsif_s *)(arg);
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/* In this port for FreeRTOS+TCP, the EMAC interrupts will only set a bit in
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"isr_events". The task in NetworkInterface will wake-up and do the necessary work.
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*/
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xemacpsif->isr_events |= EMAC_IF_TX_EVENT;
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xemacpsif->txBusy = pdFALSE;
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if( xEMACTaskHandle != NULL )
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{
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vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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}
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portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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}
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static BaseType_t xValidLength( BaseType_t xLength )
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{
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BaseType_t xReturn;
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if( ( xLength >= ( BaseType_t ) sizeof( struct xARP_PACKET ) ) && ( ( ( uint32_t ) xLength ) <= ipTOTAL_ETHERNET_FRAME_SIZE ) )
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{
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xReturn = pdTRUE;
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}
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else
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{
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xReturn = pdFALSE;
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}
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return xReturn;
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}
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XStatus emacps_send_message(xemacpsif_s *xemacpsif, NetworkBufferDescriptor_t *pxBuffer, int iReleaseAfterSend )
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{
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int head = xemacpsif->txHead;
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//int tail = xemacpsif->txTail;
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int iHasSent = 0;
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uint32_t ulBaseAddress = xemacpsif->emacps.Config.BaseAddress;
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TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 5000u );
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#if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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{
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/* This driver wants to own all network buffers which are to be transmitted. */
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configASSERT( iReleaseAfterSend != pdFALSE );
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}
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#endif
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/* Open a do {} while ( 0 ) loop to be able to call break. */
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do
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{
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uint32_t ulFlags = 0;
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if( xValidLength( pxBuffer->xDataLength ) != pdTRUE )
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{
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break;
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}
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if( xTXDescriptorSemaphore == NULL )
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{
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break;
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}
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if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
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{
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FreeRTOS_printf( ( "emacps_send_message: Time-out waiting for TX buffer\n" ) );
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break;
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}
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#if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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/* Pass the pointer (and its ownership) directly to DMA. */
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pxDMA_tx_buffers[ head ] = pxBuffer->pucEthernetBuffer;
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if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
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{
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Xil_DCacheFlushRange( ( unsigned )pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength );
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}
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/* Buffer has been transferred, do not release it. */
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iReleaseAfterSend = pdFALSE;
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#else
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if( pxDMA_tx_buffers[ head ] == NULL )
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{
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FreeRTOS_printf( ( "emacps_send_message: pxDMA_tx_buffers[ %d ] == NULL\n", head ) );
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break;
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}
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/* Copy the message to unbuffered space in RAM. */
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memcpy( pxDMA_tx_buffers[ head ], pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength );
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#endif
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/* Packets will be sent one-by-one, so for each packet
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the TXBUF_LAST bit will be set. */
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ulFlags |= XEMACPS_TXBUF_LAST_MASK;
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ulFlags |= ( pxBuffer->xDataLength & XEMACPS_TXBUF_LEN_MASK );
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if( head == ( ipconfigNIC_N_TX_DESC - 1 ) )
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{
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ulFlags |= XEMACPS_TXBUF_WRAP_MASK;
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}
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/* Copy the address of the buffer and set the flags. */
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xemacpsif->txSegments[ head ].address = ( uint32_t )pxDMA_tx_buffers[ head ];
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xemacpsif->txSegments[ head ].flags = ulFlags;
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iHasSent = pdTRUE;
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if( ++head == ipconfigNIC_N_TX_DESC )
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{
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head = 0;
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}
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/* Update the TX-head index. These variable are declared volatile so they will be
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accessed as little as possible. */
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xemacpsif->txHead = head;
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} while( pdFALSE );
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if( iReleaseAfterSend != pdFALSE )
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{
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vReleaseNetworkBufferAndDescriptor( pxBuffer );
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pxBuffer = NULL;
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}
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/* Data Synchronization Barrier */
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dsb();
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if( iHasSent != pdFALSE )
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{
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/* Make STARTTX high */
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uint32_t ulValue = XEmacPs_ReadReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET);
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/* Start transmit */
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xemacpsif->txBusy = pdTRUE;
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XEmacPs_WriteReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET, ( ulValue | XEMACPS_NWCTRL_STARTTX_MASK ) );
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}
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dsb();
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return 0;
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}
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void emacps_recv_handler(void *arg)
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{
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xemacpsif_s *xemacpsif;
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BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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xemacpsif = (xemacpsif_s *)(arg);
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xemacpsif->isr_events |= EMAC_IF_RX_EVENT;
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if( xEMACTaskHandle != NULL )
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{
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vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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}
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portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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}
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static void passEthMessages( NetworkBufferDescriptor_t *ethMsg )
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{
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IPStackEvent_t xRxEvent;
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xRxEvent.eEventType = eNetworkRxEvent;
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xRxEvent.pvData = ( void * ) ethMsg;
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if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS )
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{
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/* The buffer could not be sent to the stack so must be released again.
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This is a deferred handler taskr, not a real interrupt, so it is ok to
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use the task level function here. */
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do
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{
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NetworkBufferDescriptor_t *xNext = ethMsg->pxNextBuffer;
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vReleaseNetworkBufferAndDescriptor( ethMsg );
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ethMsg = xNext;
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} while( ethMsg != NULL );
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iptraceETHERNET_RX_EVENT_LOST();
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FreeRTOS_printf( ( "passEthMessages: Can not queue return packet!\n" ) );
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}
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}
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TickType_t ack_reception_delay = 10;
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int emacps_check_rx( xemacpsif_s *xemacpsif )
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{
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NetworkBufferDescriptor_t *pxBuffer, *pxNewBuffer;
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int rx_bytes;
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volatile int msgCount = 0;
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int head = xemacpsif->rxHead;
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BaseType_t bHasDataPacket = pdFALSE;
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NetworkBufferDescriptor_t *ethMsg = NULL;
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NetworkBufferDescriptor_t *ethLast = NULL;
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/* There seems to be an issue (SI# 692601), see comments below. */
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resetrx_on_no_rxdata(xemacpsif);
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{
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static int maxcount = 0;
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int count = 0;
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for( ;; )
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{
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if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) ||
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( pxDMA_rx_buffers[ head ] == NULL ) )
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{
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break;
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}
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count++;
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if( ++head == ipconfigNIC_N_RX_DESC )
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{
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head = 0;
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}
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if( head == xemacpsif->rxHead )
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{
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break;
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}
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}
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if (maxcount < count) {
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maxcount = count;
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FreeRTOS_printf( ( "emacps_check_rx: %d packets\n", maxcount ) );
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}
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head = xemacpsif->rxHead;
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}
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/* This FreeRTOS+TCP driver shall be compiled with the option
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"ipconfigUSE_LINKED_RX_MESSAGES" enabled. It allows the driver to send a
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chain of RX messages within one message to the IP-task. */
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for( ;; )
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{
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if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) ||
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( pxDMA_rx_buffers[ head ] == NULL ) )
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{
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break;
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}
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pxNewBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 );
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if( pxNewBuffer == NULL )
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{
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/* A packet has been received, but there is no replacement for this Network Buffer.
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The packet will be dropped, and it Network Buffer will stay in place. */
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FreeRTOS_printf( ("emacps_check_rx: unable to allocate a Netwrok Buffer\n" ) );
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pxNewBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ];
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}
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else
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{
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pxBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ];
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/* Just avoiding to use or refer to the same buffer again */
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pxDMA_rx_buffers[ head ] = pxNewBuffer;
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/*
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* Adjust the buffer size to the actual number of bytes received.
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*/
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rx_bytes = xemacpsif->rxSegments[ head ].flags & XEMACPS_RXBUF_LEN_MASK;
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pxBuffer->xDataLength = rx_bytes;
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if( rx_bytes > 60 )
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{
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bHasDataPacket = 1;
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}
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if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
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{
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Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)rx_bytes );
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}
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/* store it in the receive queue, where it'll be processed by a
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different handler. */
|
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iptraceNETWORK_INTERFACE_RECEIVE();
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pxBuffer->pxNextBuffer = NULL;
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|
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if( ethMsg == NULL )
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{
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// Becomes the first message
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ethMsg = pxBuffer;
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}
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else if( ethLast != NULL )
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{
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// Add to the tail
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ethLast->pxNextBuffer = pxBuffer;
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}
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ethLast = pxBuffer;
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msgCount++;
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}
|
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{
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if( ucIsCachedMemory( pxNewBuffer->pucEthernetBuffer ) != 0 )
|
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{
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Xil_DCacheInvalidateRange( ( ( uint32_t )pxNewBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)ipTOTAL_ETHERNET_FRAME_SIZE );
|
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}
|
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{
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uint32_t addr = ( ( uint32_t )pxNewBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK;
|
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if( head == ( ipconfigNIC_N_RX_DESC - 1 ) )
|
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{
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addr |= XEMACPS_RXBUF_WRAP_MASK;
|
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}
|
|
/* Clearing 'XEMACPS_RXBUF_NEW_MASK' 0x00000001 *< Used bit.. */
|
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xemacpsif->rxSegments[ head ].flags = 0;
|
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xemacpsif->rxSegments[ head ].address = addr;
|
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if (xemacpsif->rxSegments[ head ].address) {
|
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// Just to read it
|
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}
|
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}
|
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}
|
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|
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if( ++head == ipconfigNIC_N_RX_DESC )
|
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{
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head = 0;
|
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}
|
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xemacpsif->rxHead = head;
|
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}
|
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|
|
if( ethMsg != NULL )
|
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{
|
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if( bHasDataPacket == pdFALSE )
|
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{
|
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// vTaskDelay( ack_reception_delay );
|
|
}
|
|
passEthMessages( ethMsg );
|
|
}
|
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|
|
return msgCount;
|
|
}
|
|
|
|
void clean_dma_txdescs(xemacpsif_s *xemacpsif)
|
|
{
|
|
int index;
|
|
unsigned char *ucTxBuffer;
|
|
|
|
/* Clear all TX descriptors and assign uncached memory to each descriptor.
|
|
"tx_space" points to the first available TX buffer. */
|
|
ucTxBuffer = xemacpsif->tx_space;
|
|
|
|
for( index = 0; index < ipconfigNIC_N_TX_DESC; index++ )
|
|
{
|
|
xemacpsif->txSegments[ index ].address = ( uint32_t )ucTxBuffer;
|
|
xemacpsif->txSegments[ index ].flags = XEMACPS_TXBUF_USED_MASK;
|
|
#if( ipconfigZERO_COPY_TX_DRIVER != 0 )
|
|
pxDMA_tx_buffers[ index ] = ( unsigned char * )NULL;
|
|
#else
|
|
pxDMA_tx_buffers[ index ] = ( unsigned char * )( ucTxBuffer + TX_OFFSET );
|
|
#endif
|
|
ucTxBuffer += xemacpsif->uTxUnitSize;
|
|
}
|
|
xemacpsif->txSegments[ ipconfigNIC_N_TX_DESC - 1 ].flags =
|
|
XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK;
|
|
}
|
|
|
|
XStatus init_dma(xemacpsif_s *xemacpsif)
|
|
{
|
|
NetworkBufferDescriptor_t *pxBuffer;
|
|
|
|
int iIndex;
|
|
UBaseType_t xRxSize;
|
|
UBaseType_t xTxSize;
|
|
struct xtopology_t *xtopologyp = &xXTopology;
|
|
|
|
xRxSize = ipconfigNIC_N_RX_DESC * sizeof( xemacpsif->rxSegments[ 0 ] );
|
|
|
|
xTxSize = ipconfigNIC_N_TX_DESC * sizeof( xemacpsif->txSegments[ 0 ] );
|
|
|
|
/* Also round-up to 4KB */
|
|
xemacpsif->uTxUnitSize = ( ipTOTAL_ETHERNET_FRAME_SIZE + 0x1000ul ) & ~0xffful;
|
|
/*
|
|
* We allocate 65536 bytes for RX BDs which can accommodate a
|
|
* maximum of 8192 BDs which is much more than any application
|
|
* will ever need.
|
|
*/
|
|
xemacpsif->rxSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xRxSize ) );
|
|
xemacpsif->txSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xTxSize ) );
|
|
xemacpsif->tx_space = ( unsigned char * )( pucGetUncachedMemory ( ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize ) );
|
|
|
|
/* These variables will be used in XEmacPs_Start (see src/xemacps.c). */
|
|
xemacpsif->emacps.RxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->rxSegments;
|
|
xemacpsif->emacps.TxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->txSegments;
|
|
|
|
if( xTXDescriptorSemaphore == NULL )
|
|
{
|
|
xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ipconfigNIC_N_TX_DESC, ( UBaseType_t ) ipconfigNIC_N_TX_DESC );
|
|
configASSERT( xTXDescriptorSemaphore );
|
|
}
|
|
/*
|
|
* Allocate RX descriptors, 1 RxBD at a time.
|
|
*/
|
|
for( iIndex = 0; iIndex < ipconfigNIC_N_RX_DESC; iIndex++ )
|
|
{
|
|
pxBuffer = pxDMA_rx_buffers[ iIndex ];
|
|
if( pxBuffer == NULL )
|
|
{
|
|
pxBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 );
|
|
if( pxBuffer == NULL )
|
|
{
|
|
FreeRTOS_printf( ("Unable to allocate a network buffer in recv_handler\n" ) );
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
xemacpsif->rxSegments[ iIndex ].flags = 0;
|
|
xemacpsif->rxSegments[ iIndex ].address = ( ( uint32_t )pxBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK;
|
|
|
|
pxDMA_rx_buffers[ iIndex ] = pxBuffer;
|
|
/* Make sure this memory is not in cache for now. */
|
|
if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
|
|
{
|
|
Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE,
|
|
(unsigned)ipTOTAL_ETHERNET_FRAME_SIZE );
|
|
}
|
|
}
|
|
|
|
xemacpsif->rxSegments[ ipconfigNIC_N_RX_DESC - 1 ].address |= XEMACPS_RXBUF_WRAP_MASK;
|
|
|
|
memset( xemacpsif->tx_space, '\0', ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize );
|
|
|
|
clean_dma_txdescs( xemacpsif );
|
|
|
|
{
|
|
uint32_t value;
|
|
value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET );
|
|
|
|
// 1xxxx: Attempt to use INCR16 AHB bursts
|
|
value = ( value & ~( XEMACPS_DMACR_BLENGTH_MASK ) ) | XEMACPS_DMACR_INCR16_AHB_BURST;
|
|
#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
|
|
value |= XEMACPS_DMACR_TCPCKSUM_MASK;
|
|
#else
|
|
#warning Are you sure the EMAC should not calculate outgoing checksums?
|
|
value &= ~XEMACPS_DMACR_TCPCKSUM_MASK;
|
|
#endif
|
|
XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET, value );
|
|
}
|
|
{
|
|
uint32_t value;
|
|
value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET );
|
|
|
|
/* Network buffers are 32-bit aligned + 2 bytes (because ipconfigPACKET_FILLER_SIZE = 2 ).
|
|
Now tell the EMAC that received messages should be stored at "address + 2". */
|
|
value = ( value & ~XEMACPS_NWCFG_RXOFFS_MASK ) | 0x8000;
|
|
|
|
#if( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 )
|
|
value |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
|
|
#else
|
|
#warning Are you sure the EMAC should not calculate incoming checksums?
|
|
value &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK;
|
|
#endif
|
|
XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET, value );
|
|
}
|
|
|
|
/*
|
|
* Connect the device driver handler that will be called when an
|
|
* interrupt for the device occurs, the handler defined above performs
|
|
* the specific interrupt processing for the device.
|
|
*/
|
|
XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr,
|
|
(Xil_ExceptionHandler)XEmacPs_IntrHandler,
|
|
(void *)&xemacpsif->emacps);
|
|
/*
|
|
* Enable the interrupt for emacps.
|
|
*/
|
|
EmacEnableIntr( );
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* resetrx_on_no_rxdata():
|
|
*
|
|
* It is called at regular intervals through the API xemacpsif_resetrx_on_no_rxdata
|
|
* called by the user.
|
|
* The EmacPs has a HW bug (SI# 692601) on the Rx path for heavy Rx traffic.
|
|
* Under heavy Rx traffic because of the HW bug there are times when the Rx path
|
|
* becomes unresponsive. The workaround for it is to check for the Rx path for
|
|
* traffic (by reading the stats registers regularly). If the stats register
|
|
* does not increment for sometime (proving no Rx traffic), the function resets
|
|
* the Rx data path.
|
|
*
|
|
*/
|
|
|
|
void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif)
|
|
{
|
|
unsigned long regctrl;
|
|
unsigned long tempcntr;
|
|
|
|
tempcntr = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET );
|
|
if ( ( tempcntr == 0 ) && ( xemacpsif->last_rx_frms_cntr == 0 ) )
|
|
{
|
|
FreeRTOS_printf( ( "resetrx_on_no_rxdata: RESET~\n" ) );
|
|
regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
|
|
XEMACPS_NWCTRL_OFFSET);
|
|
regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
|
|
XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
|
|
XEMACPS_NWCTRL_OFFSET, regctrl);
|
|
regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
|
|
regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
|
|
XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
|
|
}
|
|
xemacpsif->last_rx_frms_cntr = tempcntr;
|
|
}
|
|
|
|
void EmacDisableIntr(void)
|
|
{
|
|
XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr);
|
|
}
|
|
|
|
void EmacEnableIntr(void)
|
|
{
|
|
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr);
|
|
}
|
|
|