422 lines
12 KiB
C
422 lines
12 KiB
C
/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ST STR91x ARM9
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* port.
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*----------------------------------------------------------*/
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/* Library includes. */
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#include "91x_lib.h"
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/* Standard includes. */
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#include <stdlib.h>
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#include <assert.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configUSE_WATCHDOG_TICK
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#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
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#endif
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/* Constants required to setup the initial stack. */
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#ifndef _RUN_TASK_IN_ARM_MODE_
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#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
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#else
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#endif
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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#ifndef abs
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#define abs(x) ((x)>0 ? (x) : -(x))
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#endif
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/**
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* Toggle a led using the following algorithm:
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* if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
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* {
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* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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* }
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* else
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* {
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* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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* }
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*
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*/
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#define TOGGLE_LED(port,pin) \
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if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
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{ \
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(port)->DR[(pin) <<2] = 0x00; \
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} \
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else \
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{ \
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(port)->DR[(pin) <<2] = (pin); \
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}
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/*-----------------------------------------------------------*/
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/* Setup the watchdog to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/* ulCriticalNesting will get set to zero when the first task starts. It
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cannot be initialised to 0 as this will cause interrupts to be enabled
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during the kernel initialisation process. */
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uint32_t ulCriticalNesting = ( uint32_t ) 9999;
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/* Tick interrupt routines for cooperative and preemptive operation
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respectively. The preemptive version is not defined as __irq as it is called
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from an asm wrapper function. */
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void WDG_IRQHandler( void );
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/* VIC interrupt default handler. */
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static void prvDefaultHandler( void );
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#if configUSE_WATCHDOG_TICK == 0
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/* Used to update the OCR timer register */
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static u16 s_nPulseLength;
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#endif
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been called.
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*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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StackType_t *pxOriginalTOS;
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pxOriginalTOS = pxTopOfStack;
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/* To ensure asserts in tasks.c don't fail, although in this case the assert
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is not really required. */
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pxTopOfStack--;
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/* Setup the initial stack of the task. The stack is set exactly as
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expected by the portRESTORE_CONTEXT() macro. */
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/* First on the stack is the return address - which in this case is the
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start of the task. The offset is added to make the return address appear
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as it would within an IRQ ISR. */
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*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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/* When the task starts is will expect to find the function parameter in
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R0. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* The status register is set for system mode, with interrupts enabled. */
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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pxTopOfStack--;
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/* Interrupt flags cannot always be stored on the stack and will
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instead be stored in a variable, which is then saved as part of the
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tasks context. */
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void vPortStartFirstTask( void );
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Start the first task. */
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the ARM port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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/* This function is called from an asm wrapper, so does not require the __irq
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keyword. */
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#if configUSE_WATCHDOG_TICK == 1
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static void prvFindFactors(u32 n, u16 *a, u32 *b)
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{
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/* This function is copied from the ST STR7 library and is
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copyright STMicroelectronics. Reproduced with permission. */
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u32 b0;
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u16 a0;
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int32_t err, err_min=n;
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*a = a0 = ((n-1)/65536ul) + 1;
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*b = b0 = n / *a;
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for (; *a <= 256; (*a)++)
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{
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*b = n / *a;
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err = (int32_t)*a * (int32_t)*b - (int32_t)n;
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if (abs(err) > (*a / 2))
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{
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(*b)++;
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err = (int32_t)*a * (int32_t)*b - (int32_t)n;
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}
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if (abs(err) < abs(err_min))
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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if (err == 0) break;
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}
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}
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*a = a0;
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*b = b0;
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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WDG_InitTypeDef xWdg;
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uint16_t a;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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/* Configure the watchdog as a free running timer that generates a
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periodic interrupt. */
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SCU_APBPeriphClockConfig( __WDG, ENABLE );
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WDG_DeInit();
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WDG_StructInit(&xWdg);
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prvFindFactors( n, &a, &b );
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xWdg.WDG_Prescaler = a - 1;
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xWdg.WDG_Preload = b - 1;
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WDG_Init( &xWdg );
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WDG_ITConfig(ENABLE);
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/* Configure the VIC for the WDG interrupt. */
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VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
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VIC_ITCmd( WDG_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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WDG_Cmd(ENABLE);
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}
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/*-----------------------------------------------------------*/
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void WDG_IRQHandler( void )
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{
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{
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/* Increment the tick counter. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Select a new task to execute. */
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vTaskSwitchContext();
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}
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/* Clear the interrupt in the watchdog. */
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WDG->SR &= ~0x0001;
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}
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}
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#else
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static void prvFindFactors(u32 n, u8 *a, u16 *b)
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{
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/* This function is copied from the ST STR7 library and is
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copyright STMicroelectronics. Reproduced with permission. */
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u16 b0;
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u8 a0;
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int32_t err, err_min=n;
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*a = a0 = ((n-1)/256) + 1;
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*b = b0 = n / *a;
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for (; *a <= 256; (*a)++)
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{
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*b = n / *a;
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err = (int32_t)*a * (int32_t)*b - (int32_t)n;
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if (abs(err) > (*a / 2))
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{
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(*b)++;
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err = (int32_t)*a * (int32_t)*b - (int32_t)n;
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}
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if (abs(err) < abs(err_min))
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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if (err == 0) break;
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}
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}
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*a = a0;
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*b = b0;
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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uint8_t a;
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uint16_t b;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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TIM_InitTypeDef timer;
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SCU_APBPeriphClockConfig( __TIM23, ENABLE );
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TIM_DeInit(TIM2);
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TIM_StructInit(&timer);
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prvFindFactors( n, &a, &b );
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timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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timer.TIM_OC1_Modes = TIM_TIMING;
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timer.TIM_Clock_Source = TIM_CLK_APB;
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timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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timer.TIM_Prescaler = a-1;
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timer.TIM_Pulse_Level_1 = TIM_HIGH;
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timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
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TIM_Init (TIM2, &timer);
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TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
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/* Configure the VIC for the WDG interrupt. */
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VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
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VIC_ITCmd( TIM2_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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TIM_CounterCmd(TIM2, TIM_CLEAR);
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TIM_CounterCmd(TIM2, TIM_START);
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}
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/*-----------------------------------------------------------*/
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void TIM2_IRQHandler( void )
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{
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/* Reset the timer counter to avioid overflow. */
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TIM2->OC1R += s_nPulseLength;
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/* Increment the tick counter. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Select a new task to run. */
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vTaskSwitchContext();
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}
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/* Clear the interrupt in the watchdog. */
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TIM2->SR &= ~TIM_FLAG_OC1;
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}
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#endif /* USE_WATCHDOG_TICK */
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/*-----------------------------------------------------------*/
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__arm __interwork void vPortEnterCritical( void )
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{
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/* Disable interrupts first! */
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portDISABLE_INTERRUPTS();
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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__arm __interwork void vPortExitCritical( void )
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{
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if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as we are leaving a critical section. */
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ulCriticalNesting--;
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/* If the nesting level has reached zero then interrupts should be
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re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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portENABLE_INTERRUPTS();
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}
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}
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}
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/*-----------------------------------------------------------*/
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static void prvDefaultHandler( void )
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{
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}
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