2325 lines
82 KiB
JSON
2325 lines
82 KiB
JSON
{
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"schemaVersion": "0.2.4",
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"contentVersion": "0.2.0",
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"headerVersion": "0.2.0",
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"device": {
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"fe310": {
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"displayName": "Freedom E310-G000",
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"description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
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"supplier": {
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"name": "sifive",
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"id": "1",
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"displayName": "SiFive",
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"fullName": "SiFive, Inc.",
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"contact": "info@sifive.com"
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},
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"busWidth": "32",
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"resetMask": "all",
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"resetValue": "0x00000000",
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"access": "rw",
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"headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
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"headerTypePrefix": "sifive_fe310_",
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"headerInterruptPrefix": "sifive_fe310_interrupt_global_",
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"headerInterruptEnumPrefix": "riscv_interrupts_global_",
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"revision": "r0p0",
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"numInterrupts": "51",
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"priorityBits": "3",
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"regWidth": "32",
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"cores": {
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"e31": {
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"harts": "1",
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"isa": "RV32IMAC",
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"isaVersion": "2.2",
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"mpu": "pmp",
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"mmu": "none",
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"localInterrupts": {
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"machine_software": {
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"description": "Machine Software Interrupt",
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"value": "3"
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},
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"machine_timer": {
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"description": "Machine Timer Interrupt",
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"value": "7"
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},
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"machine_ext": {
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"description": "Machine External Interrupt",
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"value": "11"
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}
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},
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"numLocalInterrupts": "0"
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}
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},
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"peripherals": {
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"clint": {
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"description": "Core Complex Local Interruptor (CLINT) Peripheral",
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"baseAddress": "0x02000000",
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"size": "0x10000",
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"registers": {
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"msip": {
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"description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
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"addressOffset": "0x0000",
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"arraySize": "1"
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}
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},
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"clusters": {
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"mtimecmp": {
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"description": "Machine Time Compare Registers per Hart",
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"addressOffset": "0x4000",
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"arraySize": "1",
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"registers": {
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"low": {
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"description": "Machine Compare Register Low",
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"addressOffset": "0x0000"
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},
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"high": {
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"description": "Machine Compare Register High",
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"addressOffset": "0x0004"
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}
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}
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},
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"mtime": {
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"description": "Machine Time Register",
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"addressOffset": "0xBFF8",
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"access": "r",
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"registers": {
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"low": {
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"description": "Machine Time Register Low",
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"addressOffset": "0x0000"
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},
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"high": {
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"description": "Machine Time Register High",
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"addressOffset": "0x0004"
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}
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}
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}
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}
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},
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"plic": {
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"description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
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"baseAddress": "0x0C000000",
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"size": "0x4000000",
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"registers": {
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"priorities": {
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"arraySize": "52",
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"description": "Interrupt Priorities Registers; 0 is reserved.",
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"addressOffset": "0x0000",
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"fields": {
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"value": {
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"description": "The priority for a given global interrupt",
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"bitOffset": "0",
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"bitWidth": "3",
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"resetMask": "all",
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"resetValue": "0x0"
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}
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}
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},
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"pendings": {
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"arraySize": "2",
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"description": "Interrupt Pending Bits Registers",
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"addressOffset": "0x1000",
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"access": "r"
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}
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},
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"clusters": {
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"enablestarget0": {
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"description": "Hart 0 Interrupt Enable Bits",
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"addressOffset": "0x00002000",
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"clusters": {
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"m": {
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"addressOffset": "0x0000",
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"description": "Hart 0 M-mode Interrupt Enable Bits",
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"registers": {
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"enables": {
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"arraySize": "2",
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"description": "Interrupt Enable Bits Registers",
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"addressOffset": "0x0000"
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}
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}
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}
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}
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},
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"target0": {
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"description": "Hart 0 Interrupt Thresholds",
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"addressOffset": "0x00200000",
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"clusters": {
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"m": {
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"addressOffset": "0x0000",
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"description": "Hart 0 M-Mode Interrupt Threshold",
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"registers": {
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"threshold": {
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"description": "The Priority Threshold Register",
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"addressOffset": "0x0000",
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"fields": {
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"value": {
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"description": "The priority threshold value",
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"bitOffset": "0",
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"bitWidth": "3",
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"resetMask": "all",
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"resetValue": "0x0"
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}
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}
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},
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"claimcomplete": {
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"description": "The Interrupt Claim/Completion Register",
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"addressOffset": "0x0004"
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}
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}
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}
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}
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}
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}
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},
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"wdog": {
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"description": "Watchdog Timer (WDT), part of Always-On Domain",
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"baseAddress": "0x10000000",
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"size": "0x0040",
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"resetMask": "none",
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"registers": {
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"cfg": {
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"description": "Watchdog Configuration Register",
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"addressOffset": "0x0000",
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"fields": {
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"scale": {
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"description": "Watchdog counter scale",
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"bitOffset": "0",
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"bitWidth": "4"
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},
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"rsten": {
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"description": "Watchdog full reset enable",
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"bitOffset": "8",
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"bitWidth": "1",
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"resetMask": "all",
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"resetValue": "0x0"
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},
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"zerocmp": {
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"description": "Watchdog zero on comparator",
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"bitOffset": "9",
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"bitWidth": "1"
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},
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"enalways": {
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"description": "Watchdog enable counter always",
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"bitOffset": "12",
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"bitWidth": "1",
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"resetMask": "all",
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"resetValue": "0x0"
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},
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"encoreawake": {
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"description": "Watchdog counter only when awake",
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"bitOffset": "13",
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"bitWidth": "1",
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"resetMask": "all",
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"resetValue": "0x0"
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},
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"cmpip": {
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"description": "Watchdog interrupt pending",
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"bitOffset": "28",
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"bitWidth": "1"
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}
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}
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},
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"count": {
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"description": "Watchdog Count Register",
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"addressOffset": "0x0008"
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},
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"scale": {
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"description": "Watchdog Scale Register",
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"addressOffset": "0x0010",
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"fields": {
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"value": {
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"description": "Watchdog scale value",
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"bitOffset": "0",
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"bitWidth": "16"
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}
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}
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},
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"feed": {
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"description": "Watchdog Feed Address Register",
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"addressOffset": "0x0018"
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},
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"key": {
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"description": "Watchdog Key Register",
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"addressOffset": "0x001C"
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},
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"cmp": {
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"description": "Watchdog Compare Register",
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"addressOffset": "0x0020",
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"fields": {
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"value": {
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"description": "Watchdog compare value",
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"bitOffset": "0",
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"bitWidth": "16"
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}
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}
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}
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},
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"interrupts": {
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"wdogcmp": {
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"description": "Watchdog Compare Interrupt",
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"value": "1"
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}
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}
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},
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"rtc": {
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"description": "Real-Time Clock (RTC), part of Always-On Domain",
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"baseAddress": "0x10000040",
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"size": "0x0030",
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"resetMask": "none",
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"registers": {
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"cfg": {
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"description": "RTC Configuration Register",
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"addressOffset": "0x0000",
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"fields": {
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"scale": {
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"description": "RTC clock rate scale",
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"bitOffset": "0",
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"bitWidth": "4"
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},
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"enalways": {
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"description": "RTC counter enable",
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"bitOffset": "12",
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"bitWidth": "1",
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"resetMask": "all",
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"resetValue": "0x0"
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},
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"cmpip": {
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"description": "RTC comparator interrupt pending",
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"bitOffset": "28",
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"bitWidth": "1",
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"access": "r"
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}
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}
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},
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"low": {
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"description": "RTC Counter Register Low",
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"addressOffset": "0x0008"
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},
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"high": {
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"description": "RTC Counter Register High",
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"addressOffset": "0x000C",
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"fields": {
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"value": {
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"description": "RTC counter register, high bits",
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"bitOffset": "0",
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"bitWidth": "16"
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}
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}
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},
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"scale": {
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"description": "RTC Scale Register",
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"addressOffset": "0x0010"
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},
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"cmp": {
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"description": "RTC Compare Register",
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"addressOffset": "0x0020"
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}
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},
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"interrupts": {
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"rtccmp": {
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"description": "RTC Compare Interrupt",
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"value": "2"
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}
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}
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},
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"pmu": {
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"description": "Power-Management Unit (PMU), part of Always-On Domain",
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"baseAddress": "0x10000100",
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"size": "0x0050",
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"resetMask": "none",
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"registers": {
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"wakeupi": {
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"description": "Wakeup program instruction Registers",
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"addressOffset": "0x0000",
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"arraySize": "8"
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},
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"sleepi": {
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"description": "Sleep Program Instruction Registers",
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"addressOffset": "0x0020",
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"arraySize": "8"
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},
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"ie": {
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"description": "PMU Interrupt Enables Register",
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"addressOffset": "0x0040",
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"fields": {
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"rtc": {
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"description": "RTC Comparator active",
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"bitOffset": "1",
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"bitWidth": "1"
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},
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"dwakeup": {
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"description": "dwakeup_n pin active",
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"bitOffset": "2",
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"bitWidth": "1"
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}
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}
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},
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"cause": {
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"description": "PMU Wakeup Cause Register",
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"addressOffset": "0x0044",
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"fields": {
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"wakeupcause": {
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"description": "Wakeup cause",
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"bitOffset": "0",
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"bitWidth": "2",
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"access": "r",
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"enumerations": {
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"wakeupcause-enum": {
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"description": "Wakeup Cause Values Enumeration",
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"values": {
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"0": {
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"displayName": "reset",
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"description": "Reset Wakeup"
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},
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"1": {
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"displayName": "rtc",
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"description": "RTC Wakeup"
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},
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"2": {
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"displayName": "dwakeup",
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"description": "Digital input Wakeup"
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},
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"*": {
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"displayName": "undefined"
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}
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}
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}
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}
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},
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"resetcause": {
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"description": "Reset cause",
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"bitOffset": "8",
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"bitWidth": "2",
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"access": "r",
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"enumerations": {
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"resetcause-enum": {
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"description": "Reset Cause Values Enumeration",
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"values": {
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"1": {
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"displayName": "external",
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"description": "External reset"
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},
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"2": {
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"displayName": "watchdog",
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"description": "Watchdog timer reset"
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},
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"*": {
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"displayName": "undefined"
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}
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}
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}
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}
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}
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}
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},
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"sleep": {
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"description": "PMU Initiate Sleep Sequence Register",
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"addressOffset": "0x0048"
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},
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"key": {
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"description": "PMU Key Register",
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"addressOffset": "0x004C"
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}
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}
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},
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"aon": {
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"description": "Always-On (AON) Domain",
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"baseAddress": "0x10000070",
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"size": "0x0090",
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"resetMask": "none",
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"registers": {
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"lfrosccfg": {
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"description": "Internal Programmable Low-Frequency Ring Oscillator Register",
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"addressOffset": "0x0000",
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"fields": {
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"div": {
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"description": "LFROSC divider",
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"bitOffset": "0",
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"bitWidth": "6",
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"resetMask": "all",
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"resetValue": "0x04"
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},
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"trim": {
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"description": "LFROSC trim value",
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"bitOffset": "16",
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"bitWidth": "5",
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"resetMask": "all",
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"resetValue": "0x10"
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},
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"en": {
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"description": "LFROSC enable",
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"bitOffset": "30",
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"bitWidth": "1",
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"resetMask": "all",
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"resetValue": "0x1"
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},
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"rdy": {
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"description": "LFROSC ready",
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"bitOffset": "31",
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"bitWidth": "1",
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"access": "r"
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}
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}
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},
|
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"backup": {
|
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"description": "Backup Registers",
|
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"addressOffset": "0x0010",
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"arraySize": "32"
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}
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}
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},
|
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"prci": {
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"description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
|
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"baseAddress": "0x10008000",
|
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"size": "0x8000",
|
|
"registers": {
|
|
"hfrosccfg": {
|
|
"description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
|
|
"addressOffset": "0x0000",
|
|
"fields": {
|
|
"div": {
|
|
"description": "HFROSC divider",
|
|
"bitOffset": "0",
|
|
"bitWidth": "6",
|
|
"resetMask": "all",
|
|
"resetValue": "0x04"
|
|
},
|
|
"trim": {
|
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"description": "HFROSC trim value",
|
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"bitOffset": "16",
|
|
"bitWidth": "5",
|
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"resetMask": "all",
|
|
"resetValue": "0x10"
|
|
},
|
|
"en": {
|
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"description": "HFROSC enable",
|
|
"bitOffset": "30",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"rdy": {
|
|
"description": "HFROSC ready",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
}
|
|
}
|
|
},
|
|
"hfxosccfg": {
|
|
"description": "External 16 MHz Crystal Oscillator Register",
|
|
"addressOffset": "0x0004",
|
|
"fields": {
|
|
"en": {
|
|
"description": "HFXOSC enable",
|
|
"bitOffset": "30",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"rdy": {
|
|
"description": "HFXOSC ready",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
}
|
|
}
|
|
},
|
|
"pllcfg": {
|
|
"description": "Internal High-Frequency PLL (HFPLL) Register",
|
|
"addressOffset": "0x0008",
|
|
"fields": {
|
|
"r": {
|
|
"description": "PLL R input divider value",
|
|
"bitOffset": "0",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1",
|
|
"enumerations": {
|
|
"pllr-enum": {
|
|
"description": "Reference Clock R Divide Ratio Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "/1",
|
|
"headerName": "div1",
|
|
"description": "Unchanged"
|
|
},
|
|
"1": {
|
|
"displayName": "/2",
|
|
"headerName": "div2",
|
|
"description": "Divided by 2"
|
|
},
|
|
"2": {
|
|
"displayName": "/3",
|
|
"headerName": "div3",
|
|
"description": "Divided by 3"
|
|
},
|
|
"3": {
|
|
"displayName": "/4",
|
|
"headerName": "div4",
|
|
"description": "Divided by 4"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"f": {
|
|
"description": "PLL F multiplier value",
|
|
"bitOffset": "4",
|
|
"bitWidth": "6",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1F",
|
|
"enumerations": {
|
|
"pllf-enum": {
|
|
"description": "Reference Clock F Multiplier Ratio Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "*2",
|
|
"headerName": "mul2",
|
|
"description": "Multiplied by 2"
|
|
},
|
|
"1": {
|
|
"displayName": "*4",
|
|
"headerName": "mul4",
|
|
"description": "Multiplied by 4"
|
|
},
|
|
"2": {
|
|
"displayName": "*6",
|
|
"headerName": "mul6",
|
|
"description": "Multiplied by 6"
|
|
},
|
|
"3": {
|
|
"displayName": "*8",
|
|
"headerName": "mul8",
|
|
"description": "Multiplied by 8"
|
|
},
|
|
"4": {
|
|
"displayName": "*10",
|
|
"headerName": "mul10",
|
|
"description": "Multiplied by 10"
|
|
},
|
|
"5": {
|
|
"displayName": "*12",
|
|
"headerName": "mul12",
|
|
"description": "Multiplied by 12"
|
|
},
|
|
"6": {
|
|
"displayName": "*14",
|
|
"headerName": "mul14",
|
|
"description": "Multiplied by 14"
|
|
},
|
|
"7": {
|
|
"displayName": "*16",
|
|
"headerName": "mul16",
|
|
"description": "Multiplied by 16"
|
|
},
|
|
"8": {
|
|
"displayName": "*18",
|
|
"headerName": "mul18",
|
|
"description": "Multiplied by 18"
|
|
},
|
|
"9": {
|
|
"displayName": "*20",
|
|
"headerName": "mul20",
|
|
"description": "Multiplied by 20"
|
|
},
|
|
"10": {
|
|
"displayName": "*22",
|
|
"headerName": "mul22",
|
|
"description": "Multiplied by 22"
|
|
},
|
|
"11": {
|
|
"displayName": "*24",
|
|
"headerName": "mul24",
|
|
"description": "Multiplied by 24"
|
|
},
|
|
"12": {
|
|
"displayName": "*26",
|
|
"headerName": "mul26",
|
|
"description": "Multiplied by 26"
|
|
},
|
|
"13": {
|
|
"displayName": "*28",
|
|
"headerName": "mul28",
|
|
"description": "Multiplied by 28"
|
|
},
|
|
"14": {
|
|
"displayName": "*30",
|
|
"headerName": "mul30",
|
|
"description": "Multiplied by 30"
|
|
},
|
|
"15": {
|
|
"displayName": "*32",
|
|
"headerName": "mul32",
|
|
"description": "Multiplied by 32"
|
|
},
|
|
"16": {
|
|
"displayName": "*34",
|
|
"headerName": "mul34",
|
|
"description": "Multiplied by 34"
|
|
},
|
|
"17": {
|
|
"displayName": "*36",
|
|
"headerName": "mul36",
|
|
"description": "Multiplied by 36"
|
|
},
|
|
"18": {
|
|
"displayName": "*38",
|
|
"headerName": "mul38",
|
|
"description": "Multiplied by 38"
|
|
},
|
|
"19": {
|
|
"displayName": "*40",
|
|
"headerName": "mul40",
|
|
"description": "Multiplied by 40"
|
|
},
|
|
"20": {
|
|
"displayName": "*42",
|
|
"headerName": "mul42",
|
|
"description": "Multiplied by 42"
|
|
},
|
|
"21": {
|
|
"displayName": "*44",
|
|
"headerName": "mul44",
|
|
"description": "Multiplied by 44"
|
|
},
|
|
"22": {
|
|
"displayName": "*46",
|
|
"headerName": "mul46",
|
|
"description": "Multiplied by 46"
|
|
},
|
|
"23": {
|
|
"displayName": "*48",
|
|
"headerName": "mul48",
|
|
"description": "Multiplied by 48"
|
|
},
|
|
"24": {
|
|
"displayName": "*50",
|
|
"headerName": "mul50",
|
|
"description": "Multiplied by 50"
|
|
},
|
|
"25": {
|
|
"displayName": "*52",
|
|
"headerName": "mul52",
|
|
"description": "Multiplied by 52"
|
|
},
|
|
"26": {
|
|
"displayName": "*54",
|
|
"headerName": "mul54",
|
|
"description": "Multiplied by 54"
|
|
},
|
|
"27": {
|
|
"displayName": "*56",
|
|
"headerName": "mul56",
|
|
"description": "Multiplied by 56"
|
|
},
|
|
"28": {
|
|
"displayName": "*58",
|
|
"headerName": "mul58",
|
|
"description": "Multiplied by 58"
|
|
},
|
|
"29": {
|
|
"displayName": "*60",
|
|
"headerName": "mul60",
|
|
"description": "Multiplied by 60"
|
|
},
|
|
"30": {
|
|
"displayName": "*62",
|
|
"headerName": "mul62",
|
|
"description": "Multiplied by 62"
|
|
},
|
|
"31": {
|
|
"displayName": "*64",
|
|
"headerName": "mul64",
|
|
"description": "Multiplied by 64"
|
|
},
|
|
"32": {
|
|
"displayName": "*66",
|
|
"headerName": "mul66",
|
|
"description": "Multiplied by 66"
|
|
},
|
|
"33": {
|
|
"displayName": "*68",
|
|
"headerName": "mul68",
|
|
"description": "Multiplied by 68"
|
|
},
|
|
"34": {
|
|
"displayName": "*70",
|
|
"headerName": "mul70",
|
|
"description": "Multiplied by 70"
|
|
},
|
|
"35": {
|
|
"displayName": "*72",
|
|
"headerName": "mul72",
|
|
"description": "Multiplied by 72"
|
|
},
|
|
"36": {
|
|
"displayName": "*74",
|
|
"headerName": "mul74",
|
|
"description": "Multiplied by 74"
|
|
},
|
|
"37": {
|
|
"displayName": "*76",
|
|
"headerName": "mul76",
|
|
"description": "Multiplied by 76"
|
|
},
|
|
"38": {
|
|
"displayName": "*78",
|
|
"headerName": "mul78",
|
|
"description": "Multiplied by 78"
|
|
},
|
|
"39": {
|
|
"displayName": "*80",
|
|
"headerName": "mul80",
|
|
"description": "Multiplied by 80"
|
|
},
|
|
"40": {
|
|
"displayName": "*82",
|
|
"headerName": "mul82",
|
|
"description": "Multiplied by 82"
|
|
},
|
|
"41": {
|
|
"displayName": "*84",
|
|
"headerName": "mul84",
|
|
"description": "Multiplied by 84"
|
|
},
|
|
"42": {
|
|
"displayName": "*86",
|
|
"headerName": "mul86",
|
|
"description": "Multiplied by 86"
|
|
},
|
|
"43": {
|
|
"displayName": "*88",
|
|
"headerName": "mul88",
|
|
"description": "Multiplied by 88"
|
|
},
|
|
"44": {
|
|
"displayName": "*90",
|
|
"headerName": "mul90",
|
|
"description": "Multiplied by 90"
|
|
},
|
|
"45": {
|
|
"displayName": "*92",
|
|
"headerName": "mul92",
|
|
"description": "Multiplied by 92"
|
|
},
|
|
"46": {
|
|
"displayName": "*94",
|
|
"headerName": "mul94",
|
|
"description": "Multiplied by 94"
|
|
},
|
|
"47": {
|
|
"displayName": "*96",
|
|
"headerName": "mul96",
|
|
"description": "Multiplied by 96"
|
|
},
|
|
"48": {
|
|
"displayName": "*98",
|
|
"headerName": "mul98",
|
|
"description": "Multiplied by 98"
|
|
},
|
|
"49": {
|
|
"displayName": "*100",
|
|
"headerName": "mul100",
|
|
"description": "Multiplied by 100"
|
|
},
|
|
"50": {
|
|
"displayName": "*102",
|
|
"headerName": "mul102",
|
|
"description": "Multiplied by 102"
|
|
},
|
|
"51": {
|
|
"displayName": "*104",
|
|
"headerName": "mul104",
|
|
"description": "Multiplied by 104"
|
|
},
|
|
"52": {
|
|
"displayName": "*106",
|
|
"headerName": "mul106",
|
|
"description": "Multiplied by 106"
|
|
},
|
|
"53": {
|
|
"displayName": "*108",
|
|
"headerName": "mul108",
|
|
"description": "Multiplied by 108"
|
|
},
|
|
"54": {
|
|
"displayName": "*110",
|
|
"headerName": "mul110",
|
|
"description": "Multiplied by 110"
|
|
},
|
|
"55": {
|
|
"displayName": "*112",
|
|
"headerName": "mul112",
|
|
"description": "Multiplied by 112"
|
|
},
|
|
"56": {
|
|
"displayName": "*114",
|
|
"headerName": "mul114",
|
|
"description": "Multiplied by 114"
|
|
},
|
|
"57": {
|
|
"displayName": "*116",
|
|
"headerName": "mul116",
|
|
"description": "Multiplied by 116"
|
|
},
|
|
"58": {
|
|
"displayName": "*118",
|
|
"headerName": "mul118",
|
|
"description": "Multiplied by 118"
|
|
},
|
|
"59": {
|
|
"displayName": "*120",
|
|
"headerName": "mul120",
|
|
"description": "Multiplied by 120"
|
|
},
|
|
"60": {
|
|
"displayName": "*122",
|
|
"headerName": "mul122",
|
|
"description": "Multiplied by 122"
|
|
},
|
|
"61": {
|
|
"displayName": "*124",
|
|
"headerName": "mul124",
|
|
"description": "Multiplied by 124"
|
|
},
|
|
"62": {
|
|
"displayName": "*126",
|
|
"headerName": "mul126",
|
|
"description": "Multiplied by 126"
|
|
},
|
|
"63": {
|
|
"displayName": "*128",
|
|
"headerName": "mul128",
|
|
"description": "Multiplied by 128"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"q": {
|
|
"description": "PLL Q output divider value",
|
|
"bitOffset": "10",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x3",
|
|
"enumerations": {
|
|
"pllq-enum": {
|
|
"description": "Reference Clock Q Divide Ratio Enumeration",
|
|
"values": {
|
|
"*": {
|
|
"displayName": "n/a",
|
|
"description": "Not supported"
|
|
},
|
|
"1": {
|
|
"displayName": "/2",
|
|
"headerName": "div2",
|
|
"description": "Divided by 2"
|
|
},
|
|
"2": {
|
|
"displayName": "/4",
|
|
"headerName": "div4",
|
|
"description": "Divided by 4"
|
|
},
|
|
"3": {
|
|
"displayName": "/8",
|
|
"headerName": "div8",
|
|
"description": "Divided by 8"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"sel": {
|
|
"description": "PLL select",
|
|
"bitOffset": "16",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"refsel": {
|
|
"description": "PLL reference select",
|
|
"bitOffset": "17",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"bypass": {
|
|
"description": "PLL bypass",
|
|
"bitOffset": "18",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"lock": {
|
|
"description": "PLL lock indicator",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
}
|
|
}
|
|
},
|
|
"plloutdiv": {
|
|
"description": "PLL Output Divider",
|
|
"addressOffset": "0x000C"
|
|
}
|
|
}
|
|
},
|
|
"otp": {
|
|
"description": "One-Time Programmable Memory (OTP) Peripheral",
|
|
"baseAddress": "0x10010000",
|
|
"size": "0x1000",
|
|
"registers": {
|
|
"lock": {
|
|
"description": "Programmed-I/O Lock Register",
|
|
"addressOffset": "0x0000"
|
|
},
|
|
"ck": {
|
|
"description": "Device Clock Signal Register",
|
|
"addressOffset": "0x0004"
|
|
},
|
|
"oe": {
|
|
"description": "Device Output-Enable Signal Register",
|
|
"addressOffset": "0x0008"
|
|
},
|
|
"sel": {
|
|
"description": "Device Chip-Select Signal Register",
|
|
"addressOffset": "0x000C"
|
|
},
|
|
"we": {
|
|
"description": "Device Write-Enable Signal Register",
|
|
"addressOffset": "0x0010"
|
|
},
|
|
"mr": {
|
|
"description": "Device Mode Register",
|
|
"addressOffset": "0x0014"
|
|
},
|
|
"mrr": {
|
|
"description": "Read-Voltage Regulator Control Register",
|
|
"addressOffset": "0x0018"
|
|
},
|
|
"mpp": {
|
|
"description": "Write-Voltage Charge Pump Control Register",
|
|
"addressOffset": "0x001C"
|
|
},
|
|
"vrren": {
|
|
"description": "Read-Voltage Enable Register",
|
|
"addressOffset": "0x0020"
|
|
},
|
|
"vppen": {
|
|
"description": "Write-Voltage Enable Register",
|
|
"addressOffset": "0x0024"
|
|
},
|
|
"a": {
|
|
"description": "Device Address Register",
|
|
"addressOffset": "0x0028"
|
|
},
|
|
"d": {
|
|
"description": "Device Data Input Register",
|
|
"addressOffset": "0x002C"
|
|
},
|
|
"q": {
|
|
"description": "Device Data Output Register",
|
|
"addressOffset": "0x0030"
|
|
},
|
|
"rsctrl": {
|
|
"description": "Read Sequencer Control Register",
|
|
"addressOffset": "0x0034",
|
|
"fields": {
|
|
"scale": {
|
|
"description": "OTP timescale",
|
|
"bitOffset": "0",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"tas": {
|
|
"description": "Address setup time",
|
|
"bitOffset": "3",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"trp": {
|
|
"description": "Read pulse time",
|
|
"bitOffset": "4",
|
|
"bitWidth": "1"
|
|
},
|
|
"tracc": {
|
|
"description": "Read access time",
|
|
"bitOffset": "5",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"gpio": {
|
|
"description": "General Purpose Input/Output Controller (GPIO) Peripheral",
|
|
"baseAddress": "0x10012000",
|
|
"size": "0x1000",
|
|
"registers": {
|
|
"value": {
|
|
"description": "Pin Value Register",
|
|
"addressOffset": "0x000",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Value Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"inputen": {
|
|
"description": "Pin Input Enable Register",
|
|
"addressOffset": "0x004",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Pin Input Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"outputen": {
|
|
"description": "Pin Output Enable Register",
|
|
"addressOffset": "0x008",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Pin Output Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"port": {
|
|
"description": "Output Port Value Register",
|
|
"addressOffset": "0x00C",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Output Port Value Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"pue": {
|
|
"description": "Internal Pull-up Enable Register",
|
|
"addressOffset": "0x010",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Internal Pull-up Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"ds": {
|
|
"description": "Pin Drive Strength Register",
|
|
"addressOffset": "0x014",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Pin Drive Strength Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"riseie": {
|
|
"description": "Rise Interrupt Enable Register",
|
|
"addressOffset": "0x018",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Rise Interrupt Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"riseip": {
|
|
"description": "Rise Interrupt Pending Register",
|
|
"addressOffset": "0x01C",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Rise Interrupt Pending Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"fallie": {
|
|
"description": "Fall Interrupt Enable Register",
|
|
"addressOffset": "0x020",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Fall Interrupt Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"fallip": {
|
|
"description": "Fall Interrupt Pending Register",
|
|
"addressOffset": "0x024",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Fall Interrupt Pending Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"highie": {
|
|
"description": "High Interrupt Enable Register",
|
|
"addressOffset": "0x028",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "High Interrupt Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"highip": {
|
|
"description": "High Interrupt Pending Register",
|
|
"addressOffset": "0x02C",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "High Interrupt Pending Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"lowie": {
|
|
"description": "Low Interrupt Enable Register",
|
|
"addressOffset": "0x030",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Low Interrupt Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"lowip": {
|
|
"description": "Low Interrupt Pending Register",
|
|
"addressOffset": "0x034",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Low Interrupt Pending Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"iofen": {
|
|
"description": "HW I/O Function Enable Register",
|
|
"addressOffset": "0x038",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "HW I/O Function Enable Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"iofsel": {
|
|
"description": "HW I/O Function Select Register",
|
|
"addressOffset": "0x03C",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "HW I/O Function Select Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
},
|
|
"outxor": {
|
|
"description": "Output XOR (invert) Register",
|
|
"addressOffset": "0x040",
|
|
"fields": {
|
|
"bit": {
|
|
"repeatGenerator": "0-31",
|
|
"description": "Output XOR Bit Field",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"headerName": ""
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interrupts": {
|
|
"gpio0": {
|
|
"description": "GPIO0 Interrupt",
|
|
"value": "8"
|
|
},
|
|
"gpio1": {
|
|
"description": "GPIO1 Interrupt",
|
|
"value": "9"
|
|
},
|
|
"gpio2": {
|
|
"description": "GPIO2 Interrupt",
|
|
"value": "10"
|
|
},
|
|
"gpio3": {
|
|
"description": "GPIO3 Interrupt",
|
|
"value": "11"
|
|
},
|
|
"gpio4": {
|
|
"description": "GPIO4 Interrupt",
|
|
"value": "12"
|
|
},
|
|
"gpio5": {
|
|
"description": "GPIO5 Interrupt",
|
|
"value": "13"
|
|
},
|
|
"gpio6": {
|
|
"description": "GPIO6 Interrupt",
|
|
"value": "14"
|
|
},
|
|
"gpio7": {
|
|
"description": "GPIO7 Interrupt",
|
|
"value": "15"
|
|
},
|
|
"gpio8": {
|
|
"description": "GPIO8 Interrupt",
|
|
"value": "16"
|
|
},
|
|
"gpio9": {
|
|
"description": "GPIO9 Interrupt",
|
|
"value": "17"
|
|
},
|
|
"gpio10": {
|
|
"description": "GPIO10 Interrupt",
|
|
"value": "18"
|
|
},
|
|
"gpio11": {
|
|
"description": "GPIO11 Interrupt",
|
|
"value": "19"
|
|
},
|
|
"gpio12": {
|
|
"description": "GPIO12 Interrupt",
|
|
"value": "20"
|
|
},
|
|
"gpio13": {
|
|
"description": "GPIO13 Interrupt",
|
|
"value": "21"
|
|
},
|
|
"gpio14": {
|
|
"description": "GPIO14 Interrupt",
|
|
"value": "22"
|
|
},
|
|
"gpio15": {
|
|
"description": "GPIO15 Interrupt",
|
|
"value": "23"
|
|
},
|
|
"gpio16": {
|
|
"description": "GPIO16 Interrupt",
|
|
"value": "24"
|
|
},
|
|
"gpio17": {
|
|
"description": "GPIO17 Interrupt",
|
|
"value": "25"
|
|
},
|
|
"gpio18": {
|
|
"description": "GPIO18 Interrupt",
|
|
"value": "26"
|
|
},
|
|
"gpio19": {
|
|
"description": "GPIO19 Interrupt",
|
|
"value": "27"
|
|
},
|
|
"gpio20": {
|
|
"description": "GPIO20 Interrupt",
|
|
"value": "28"
|
|
},
|
|
"gpio21": {
|
|
"description": "GPIO21 Interrupt",
|
|
"value": "29"
|
|
},
|
|
"gpio22": {
|
|
"description": "GPIO22 Interrupt",
|
|
"value": "30"
|
|
},
|
|
"gpio23": {
|
|
"description": "GPIO23 Interrupt",
|
|
"value": "31"
|
|
},
|
|
"gpio24": {
|
|
"description": "GPIO24 Interrupt",
|
|
"value": "32"
|
|
},
|
|
"gpio25": {
|
|
"description": "GPIO25 Interrupt",
|
|
"value": "33"
|
|
},
|
|
"gpio26": {
|
|
"description": "GPIO26 Interrupt",
|
|
"value": "34"
|
|
},
|
|
"gpio27": {
|
|
"description": "GPIO27 Interrupt",
|
|
"value": "35"
|
|
},
|
|
"gpio28": {
|
|
"description": "GPIO28 Interrupt",
|
|
"value": "36"
|
|
},
|
|
"gpio29": {
|
|
"description": "GPIO29 Interrupt",
|
|
"value": "37"
|
|
},
|
|
"gpio30": {
|
|
"description": "GPIO30 Interrupt",
|
|
"value": "38"
|
|
},
|
|
"gpio31": {
|
|
"description": "GPIO31 Interrupt",
|
|
"value": "39"
|
|
}
|
|
}
|
|
},
|
|
"uart0": {
|
|
"description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
|
|
"baseAddress": "0x10013000",
|
|
"size": "0x1000",
|
|
"resetMask": "none",
|
|
"groupName": "uart",
|
|
"registers": {
|
|
"txdata": {
|
|
"description": "Transmit Data Register",
|
|
"addressOffset": "0x000",
|
|
"fields": {
|
|
"data": {
|
|
"description": "Transmit data",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8"
|
|
},
|
|
"full": {
|
|
"description": "Transmit FIFO full",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"rxdata": {
|
|
"description": "Receive Data Register",
|
|
"addressOffset": "0x004",
|
|
"resetMask": "none",
|
|
"fields": {
|
|
"data": {
|
|
"description": "Received data",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8",
|
|
"access": "r"
|
|
},
|
|
"empty": {
|
|
"description": "Receive FIFO empty",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"txctrl": {
|
|
"description": "Transmit Control Register ",
|
|
"addressOffset": "0x008",
|
|
"fields": {
|
|
"txen": {
|
|
"description": "Transmit enable",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"nstop": {
|
|
"description": "Number of stop bits",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"txcnt": {
|
|
"description": "Transmit watermark level",
|
|
"bitOffset": "16",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"rxctrl": {
|
|
"description": "Receive Control Register",
|
|
"addressOffset": "0x00C",
|
|
"fields": {
|
|
"rxen": {
|
|
"description": "Receive enable",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"rxcnt": {
|
|
"description": "Receive watermark level",
|
|
"bitOffset": "16",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"ie": {
|
|
"description": "Interrupt Enable Register",
|
|
"addressOffset": "0x010",
|
|
"fields": {
|
|
"txwm": {
|
|
"description": "Transmit watermark interrupt enable",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"rxwm": {
|
|
"description": "Receive watermark interrupt enable",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"ip": {
|
|
"description": "Interrupt Pending Register",
|
|
"addressOffset": "0x014",
|
|
"access": "r",
|
|
"fields": {
|
|
"txwm": {
|
|
"description": "Transmit watermark interrupt pending",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1"
|
|
},
|
|
"rxwm": {
|
|
"description": "Receive watermark interrupt pending",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"div": {
|
|
"description": "Baud Rate Divisor Register",
|
|
"addressOffset": "0x018",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Baud rate divisor",
|
|
"bitOffset": "0",
|
|
"bitWidth": "16",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0000FFFF"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interrupts": {
|
|
"uart0": {
|
|
"description": "UART0 Interrupt",
|
|
"value": "3"
|
|
}
|
|
}
|
|
},
|
|
"spi0": {
|
|
"description": "Serial Peripheral Interface (SPI) Peripheral",
|
|
"baseAddress": "0x10014000",
|
|
"size": "0x1000",
|
|
"resetMask": "none",
|
|
"groupName": "spi",
|
|
"registers": {
|
|
"sckdiv": {
|
|
"description": "Serial clock divisor Register",
|
|
"addressOffset": "0x000",
|
|
"fields": {
|
|
"scale": {
|
|
"description": "Divisor for serial clock",
|
|
"bitOffset": "0",
|
|
"bitWidth": "12",
|
|
"resetMask": "all",
|
|
"resetValue": "0x003"
|
|
}
|
|
}
|
|
},
|
|
"sckmode": {
|
|
"description": "Serial Clock Mode Register",
|
|
"addressOffset": "0x004",
|
|
"fields": {
|
|
"pha": {
|
|
"description": "Serial clock phase",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"pol": {
|
|
"description": "Serial clock polarity",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"csid": {
|
|
"description": "Chip Select ID Register",
|
|
"addressOffset": "0x010",
|
|
"resetMask": "all",
|
|
"resetValue": "0x00000000"
|
|
},
|
|
"csdef": {
|
|
"description": "Chip Select Default Register",
|
|
"addressOffset": "0x014",
|
|
"resetMask": "all",
|
|
"resetValue": "0x00000001"
|
|
},
|
|
"csmode": {
|
|
"description": "Chip Select Mode Register",
|
|
"addressOffset": "0x018",
|
|
"fields": {
|
|
"mode": {
|
|
"description": "Chip select mode",
|
|
"bitOffset": "0",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0",
|
|
"enumerations": {
|
|
"csmode-enum": {
|
|
"description": "Chip Select Modes Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "auto",
|
|
"description": "Assert/de-assert CS at the beginning/end of each frame"
|
|
},
|
|
"*": {
|
|
"displayName": "reserved"
|
|
},
|
|
"2": {
|
|
"displayName": "hold",
|
|
"description": "Keep CS continuously asserted after the initial frame"
|
|
},
|
|
"3": {
|
|
"displayName": "off",
|
|
"description": "Disable hardware control of the CS pin"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"delay0": {
|
|
"description": "Delay Control 0 Register",
|
|
"addressOffset": "0x028",
|
|
"fields": {
|
|
"cssck": {
|
|
"description": "CS to SCK Delay",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x01"
|
|
},
|
|
"sckcs": {
|
|
"description": "SCK to CS Delay",
|
|
"bitOffset": "16",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x01"
|
|
}
|
|
}
|
|
},
|
|
"delay1": {
|
|
"description": "Delay Control 1 Register",
|
|
"addressOffset": "0x02C",
|
|
"fields": {
|
|
"intercs": {
|
|
"description": "Minimum CS inactive time",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x01"
|
|
},
|
|
"interxfr": {
|
|
"description": "Maximum interframe delay",
|
|
"bitOffset": "16",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x01"
|
|
}
|
|
}
|
|
},
|
|
"fmt": {
|
|
"description": "Frame Format Register",
|
|
"addressOffset": "0x040",
|
|
"fields": {
|
|
"proto": {
|
|
"description": "SPI Protocol",
|
|
"bitOffset": "0",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0",
|
|
"enumerations": {
|
|
"proto-enum": {
|
|
"description": "SPI Protocol Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "single",
|
|
"description": "DQ0 (MOSI), DQ1 (MISO)"
|
|
},
|
|
"1": {
|
|
"displayName": "dual",
|
|
"description": "DQ0, DQ1"
|
|
},
|
|
"2": {
|
|
"displayName": "quad",
|
|
"description": "DQ0, DQ1, DQ2, DQ3"
|
|
},
|
|
"*": {
|
|
"displayName": "reserved"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"endian": {
|
|
"description": "SPI endianness",
|
|
"bitOffset": "2",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0",
|
|
"enumerations": {
|
|
"endian-enum": {
|
|
"description": "SPI Endianness Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "msb",
|
|
"description": "Transmit most-significant bit (MSB) first"
|
|
},
|
|
"1": {
|
|
"displayName": "lsb",
|
|
"description": "Transmit least-significant bit (LSB) first"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"dir": {
|
|
"description": "SPI I/O Direction",
|
|
"bitOffset": "3",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1",
|
|
"enumerations": {
|
|
"dir-enum": {
|
|
"description": "SPI I/O Direction Enumeration",
|
|
"values": {
|
|
"0": {
|
|
"displayName": "rx",
|
|
"description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
|
|
},
|
|
"1": {
|
|
"displayName": "tx",
|
|
"description": "The receive FIFO is not populated."
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"len": {
|
|
"description": "Number of bits per frame",
|
|
"bitOffset": "16",
|
|
"bitWidth": "4",
|
|
"resetMask": "all",
|
|
"resetValue": "0x8"
|
|
}
|
|
}
|
|
},
|
|
"txdata": {
|
|
"description": "Tx FIFO Data Register",
|
|
"addressOffset": "0x048",
|
|
"fields": {
|
|
"data": {
|
|
"description": "Transmit data",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x00"
|
|
},
|
|
"full": {
|
|
"description": "FIFO full flag",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
}
|
|
}
|
|
},
|
|
"rxdata": {
|
|
"description": "Rx FIFO Data Register",
|
|
"addressOffset": "0x04C",
|
|
"resetMask": "none",
|
|
"access": "r",
|
|
"fields": {
|
|
"data": {
|
|
"description": "Received data",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8"
|
|
},
|
|
"empty": {
|
|
"description": "FIFO empty flag",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"txmark": {
|
|
"description": "Tx FIFO Watermark Register",
|
|
"addressOffset": "0x050",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Transmit watermark",
|
|
"bitOffset": "0",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
}
|
|
}
|
|
},
|
|
"rxmark": {
|
|
"description": "Rx FIFO Watermark Register",
|
|
"addressOffset": "0x054",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Receive watermark",
|
|
"bitOffset": "0",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"fctrl": {
|
|
"description": "Flash Interface Control Register",
|
|
"addressOffset": "0x060",
|
|
"fields": {
|
|
"en": {
|
|
"description": "SPI Flash Mode Select",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
}
|
|
}
|
|
},
|
|
"ffmt": {
|
|
"description": "Flash Instruction Format Register",
|
|
"addressOffset": "0x064",
|
|
"fields": {
|
|
"cmden": {
|
|
"description": "Enable sending of command",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x1"
|
|
},
|
|
"addrlen": {
|
|
"description": "Number of address bytes(0 to 4)",
|
|
"bitOffset": "1",
|
|
"bitWidth": "3",
|
|
"resetMask": "all",
|
|
"resetValue": "0x3"
|
|
},
|
|
"padcnt": {
|
|
"description": "Number of dummy cycles",
|
|
"bitOffset": "4",
|
|
"bitWidth": "4",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"cmdproto": {
|
|
"description": "Protocol for transmitting command",
|
|
"bitOffset": "8",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"addrproto": {
|
|
"description": "Protocol for transmitting address and padding",
|
|
"bitOffset": "10",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"dataproto": {
|
|
"description": "Protocol for receiving data bytes",
|
|
"bitOffset": "12",
|
|
"bitWidth": "2",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"cmdcode": {
|
|
"description": "Value of command byte",
|
|
"bitOffset": "16",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x03"
|
|
},
|
|
"padcode": {
|
|
"description": "First 8 bits to transmit during dummy cycles",
|
|
"bitOffset": "24",
|
|
"bitWidth": "8",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"ie": {
|
|
"description": "Interrupt Enable Register",
|
|
"addressOffset": "0x070",
|
|
"fields": {
|
|
"txwm": {
|
|
"description": "Transmit watermark enable",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"access": "r",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"rxwm": {
|
|
"description": "Receive watermark enable",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1",
|
|
"access": "r",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
}
|
|
}
|
|
},
|
|
"ip": {
|
|
"description": "Interrupt Pending Register",
|
|
"addressOffset": "0x074",
|
|
"fields": {
|
|
"txwm": {
|
|
"description": "Transmit watermark pending",
|
|
"bitOffset": "0",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
},
|
|
"rxwm": {
|
|
"description": "Receive watermark pending",
|
|
"bitOffset": "1",
|
|
"bitWidth": "1",
|
|
"access": "r"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interrupts": {
|
|
"spi0": {
|
|
"description": "SPI0 Interrupt",
|
|
"value": "5"
|
|
}
|
|
}
|
|
},
|
|
"pwm0": {
|
|
"description": "Pulse-Width Modulation (PWM) Peripheral",
|
|
"baseAddress": "0x10015000",
|
|
"size": "0x1000",
|
|
"resetMask": "none",
|
|
"registers": {
|
|
"cfg": {
|
|
"description": "Configuration Register",
|
|
"addressOffset": "0x000",
|
|
"fields": {
|
|
"scale": {
|
|
"description": "Counter scale",
|
|
"bitOffset": "0",
|
|
"bitWidth": "4"
|
|
},
|
|
"sticky": {
|
|
"description": "Sticky - disallow clearing pwmcmpXip bits",
|
|
"bitOffset": "8",
|
|
"bitWidth": "1"
|
|
},
|
|
"zerocmp": {
|
|
"description": "Zero - counter resets to zero after match",
|
|
"bitOffset": "9",
|
|
"bitWidth": "1"
|
|
},
|
|
"deglitch": {
|
|
"description": "Deglitch - latch pwmcmpXip within same cycle",
|
|
"bitOffset": "10",
|
|
"bitWidth": "1"
|
|
},
|
|
"enalways": {
|
|
"description": "Enable always - run continuously",
|
|
"bitOffset": "12",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"enoneshot": {
|
|
"description": "enable one shot - run one cycle",
|
|
"bitOffset": "13",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"cmp0center": {
|
|
"description": "PWM0 Compare Center",
|
|
"bitOffset": "16",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1center": {
|
|
"description": "PWM1 Compare Center",
|
|
"bitOffset": "17",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2center": {
|
|
"description": "PWM2 Compare Center",
|
|
"bitOffset": "18",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3center": {
|
|
"description": "PWM3 Compare Center",
|
|
"bitOffset": "19",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp0gang": {
|
|
"description": "PWM0/PWM1 Compare Gang",
|
|
"bitOffset": "24",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1gang": {
|
|
"description": "PWM1/PWM2 Compare Gang",
|
|
"bitOffset": "25",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2gang": {
|
|
"description": "PWM2/PWM3 Compare Gang",
|
|
"bitOffset": "26",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3gang": {
|
|
"description": "PWM3/PWM0 Compare Gang",
|
|
"bitOffset": "27",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp0ip": {
|
|
"description": "PWM0 Interrupt Pending",
|
|
"bitOffset": "28",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1ip": {
|
|
"description": "PWM1 Interrupt Pending",
|
|
"bitOffset": "29",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2ip": {
|
|
"description": "PWM2 Interrupt Pending",
|
|
"bitOffset": "30",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3ip": {
|
|
"description": "PWM3 Interrupt Pending",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"count": {
|
|
"description": "Configuration Register",
|
|
"addressOffset": "0x008"
|
|
},
|
|
"scale": {
|
|
"description": "Scale Register",
|
|
"addressOffset": "0x010",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Compare value",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8"
|
|
}
|
|
}
|
|
},
|
|
"cmp": {
|
|
"arraySize": "4",
|
|
"description": "Compare Registers",
|
|
"addressOffset": "0x020",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Compare value",
|
|
"bitOffset": "0",
|
|
"bitWidth": "8"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interrupts": {
|
|
"pwm0cmp0": {
|
|
"description": "PWM0 Compare 0 Interrupt",
|
|
"value": "40"
|
|
},
|
|
"pwm0cmp1": {
|
|
"description": "PWM0 Compare 1 Interrupt",
|
|
"value": "41"
|
|
},
|
|
"pwm0cmp2": {
|
|
"description": "PWM0 Compare 2 Interrupt",
|
|
"value": "42"
|
|
},
|
|
"pwm0cmp3": {
|
|
"description": "PWM0 Compare 3 Interrupt",
|
|
"value": "43"
|
|
}
|
|
}
|
|
},
|
|
"uart1": {
|
|
"baseAddress": "0x10023000",
|
|
"derivedFrom": "uart0",
|
|
"groupName": "uart",
|
|
"interrupts": {
|
|
"uart1": {
|
|
"description": "UART1 Interrupt",
|
|
"value": "4"
|
|
}
|
|
}
|
|
},
|
|
"spi1": {
|
|
"baseAddress": "0x10024000",
|
|
"derivedFrom": "spi0",
|
|
"groupName": "spi",
|
|
"interrupts": {
|
|
"spi1": {
|
|
"description": "SPI1 Interrupt",
|
|
"value": "6"
|
|
}
|
|
}
|
|
},
|
|
"pwm1": {
|
|
"description": "Pulse-Width Modulation (PWM) Peripheral",
|
|
"baseAddress": "0x10025000",
|
|
"groupName": "pwm",
|
|
"size": "0x1000",
|
|
"resetMask": "none",
|
|
"groupName": "pwm",
|
|
"registers": {
|
|
"cfg": {
|
|
"description": "Configuration Register",
|
|
"addressOffset": "0x000",
|
|
"fields": {
|
|
"scale": {
|
|
"description": "Counter scale",
|
|
"bitOffset": "0",
|
|
"bitWidth": "4"
|
|
},
|
|
"sticky": {
|
|
"description": "Sticky - disallow clearing pwmcmpXip bits",
|
|
"bitOffset": "8",
|
|
"bitWidth": "1"
|
|
},
|
|
"zerocmp": {
|
|
"description": "Zero - counter resets to zero after match",
|
|
"bitOffset": "9",
|
|
"bitWidth": "1"
|
|
},
|
|
"deglitch": {
|
|
"description": "Deglitch - latch pwmcmpXip within same cycle",
|
|
"bitOffset": "10",
|
|
"bitWidth": "1"
|
|
},
|
|
"enalways": {
|
|
"description": "Enable always - run continuously",
|
|
"bitOffset": "12",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"enoneshot": {
|
|
"description": "enable one shot - run one cycle",
|
|
"bitOffset": "13",
|
|
"bitWidth": "1",
|
|
"resetMask": "all",
|
|
"resetValue": "0x0"
|
|
},
|
|
"cmp0center": {
|
|
"description": "PWM0 Compare Center",
|
|
"bitOffset": "16",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1center": {
|
|
"description": "PWM1 Compare Center",
|
|
"bitOffset": "17",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2center": {
|
|
"description": "PWM2 Compare Center",
|
|
"bitOffset": "18",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3center": {
|
|
"description": "PWM3 Compare Center",
|
|
"bitOffset": "19",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp0gang": {
|
|
"description": "PWM0/PWM1 Compare Gang",
|
|
"bitOffset": "24",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1gang": {
|
|
"description": "PWM1/PWM2 Compare Gang",
|
|
"bitOffset": "25",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2gang": {
|
|
"description": "PWM2/PWM3 Compare Gang",
|
|
"bitOffset": "26",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3gang": {
|
|
"description": "PWM3/PWM0 Compare Gang",
|
|
"bitOffset": "27",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp0ip": {
|
|
"description": "PWM0 Interrupt Pending",
|
|
"bitOffset": "28",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp1ip": {
|
|
"description": "PWM1 Interrupt Pending",
|
|
"bitOffset": "29",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp2ip": {
|
|
"description": "PWM2 Interrupt Pending",
|
|
"bitOffset": "30",
|
|
"bitWidth": "1"
|
|
},
|
|
"cmp3ip": {
|
|
"description": "PWM3 Interrupt Pending",
|
|
"bitOffset": "31",
|
|
"bitWidth": "1"
|
|
}
|
|
}
|
|
},
|
|
"count": {
|
|
"description": "Configuration Register",
|
|
"addressOffset": "0x008"
|
|
},
|
|
"scale": {
|
|
"description": "Scale Register",
|
|
"addressOffset": "0x010",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Compare value",
|
|
"bitOffset": "0",
|
|
"bitWidth": "16"
|
|
}
|
|
}
|
|
},
|
|
"cmp": {
|
|
"arraySize": "4",
|
|
"description": "Compare Registers",
|
|
"addressOffset": "0x020",
|
|
"fields": {
|
|
"value": {
|
|
"description": "Compare value",
|
|
"bitOffset": "0",
|
|
"bitWidth": "16"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interrupts": {
|
|
"pwm1cmp0": {
|
|
"description": "PWM1 Compare 0 Interrupt",
|
|
"value": "44"
|
|
},
|
|
"pwm1cmp1": {
|
|
"description": "PWM1 Compare 1 Interrupt",
|
|
"value": "45"
|
|
},
|
|
"pwm1cmp2": {
|
|
"description": "PWM1 Compare 2 Interrupt",
|
|
"value": "46"
|
|
},
|
|
"pwm1cmp3": {
|
|
"description": "PWM1 Compare 3 Interrupt",
|
|
"value": "47"
|
|
}
|
|
}
|
|
},
|
|
"spi2": {
|
|
"baseAddress": "0x10034000",
|
|
"derivedFrom": "spi0",
|
|
"groupName": "spi",
|
|
"interrupts": {
|
|
"spi2": {
|
|
"description": "SPI2 Interrupt",
|
|
"value": "7"
|
|
}
|
|
}
|
|
},
|
|
"pwm2": {
|
|
"baseAddress": "0x10035000",
|
|
"derivedFrom": "pwm1",
|
|
"groupName": "pwm",
|
|
"interrupts": {
|
|
"pwm2cmp0": {
|
|
"description": "PWM2 Compare 0 Interrupt",
|
|
"value": "48"
|
|
},
|
|
"pwm2cmp1": {
|
|
"description": "PWM2 Compare 1 Interrupt",
|
|
"value": "49"
|
|
},
|
|
"pwm2cmp2": {
|
|
"description": "PWM2 Compare 2 Interrupt",
|
|
"value": "50"
|
|
},
|
|
"pwm2cmp3": {
|
|
"description": "PWM2 Compare 3 Interrupt",
|
|
"value": "51"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |