425 lines
15 KiB
C
425 lines
15 KiB
C
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the Cygnal port.
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*----------------------------------------------------------*/
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/* Standard includes. */
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#include <string.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to setup timer 2 to produce the RTOS tick. */
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#define portCLOCK_DIVISOR ( ( uint32_t ) 12 )
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#define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff )
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#define portENABLE_TIMER ( ( uint8_t ) 0x04 )
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#define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 )
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/* The value used in the IE register when a task first starts. */
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#define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 )
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/* The value used in the PSW register when a task first starts. */
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#define portINITIAL_PSW ( ( StackType_t ) 0x00 )
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/* Macro to clear the timer 2 interrupt flag. */
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#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;
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/* Used during a context switch to store the size of the stack being copied
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to or from XRAM. */
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data static uint8_t ucStackBytes;
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/* Used during a context switch to point to the next byte in XRAM from/to which
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a RAM byte is to be copied. */
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xdata static StackType_t * data pxXRAMStack;
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/* Used during a context switch to point to the next byte in RAM from/to which
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an XRAM byte is to be copied. */
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data static StackType_t * data pxRAMStack;
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/* We require the address of the pxCurrentTCB variable, but don't want to know
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any details of its type. */
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typedef void TCB_t;
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extern volatile TCB_t * volatile pxCurrentTCB;
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/*
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* Setup the hardware to generate an interrupt off timer 2 at the required
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* frequency.
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*/
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static void prvSetupTimerInterrupt( void );
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/*-----------------------------------------------------------*/
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/*
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* Macro that copies the current stack from internal RAM to XRAM. This is
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* required as the 8051 only contains enough internal RAM for a single stack,
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* but we have a stack for every task.
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*/
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#define portCOPY_STACK_TO_XRAM() \
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{ \
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/* pxCurrentTCB points to a TCB which itself points to the location into \
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which the first stack byte should be copied. Set pxXRAMStack to point \
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to the location into which the first stack byte is to be copied. */ \
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pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
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\
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/* Set pxRAMStack to point to the first byte to be coped from the stack. */ \
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pxRAMStack = ( data StackType_t * data ) configSTACK_START; \
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\
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/* Calculate the size of the stack we are about to copy from the current \
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stack pointer value. */ \
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ucStackBytes = SP - ( configSTACK_START - 1 ); \
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\
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/* Before starting to copy the stack, store the calculated stack size so \
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the stack can be restored when the task is resumed. */ \
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*pxXRAMStack = ucStackBytes; \
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\
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/* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
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have already stored the stack size into XRAM. */ \
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while( ucStackBytes ) \
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{ \
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pxXRAMStack++; \
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*pxXRAMStack = *pxRAMStack; \
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pxRAMStack++; \
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ucStackBytes--; \
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} \
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}
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/*-----------------------------------------------------------*/
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/*
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* Macro that copies the stack of the task being resumed from XRAM into
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* internal RAM.
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*/
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#define portCOPY_XRAM_TO_STACK() \
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{ \
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/* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
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copy the data back out of XRAM and into the stack. */ \
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pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
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pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \
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\
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/* The first value stored in XRAM was the size of the stack - i.e. the \
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number of bytes we need to copy back. */ \
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ucStackBytes = pxXRAMStack[ 0 ]; \
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\
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/* Copy the required number of bytes back into the stack. */ \
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do \
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{ \
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pxXRAMStack++; \
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pxRAMStack++; \
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*pxRAMStack = *pxXRAMStack; \
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ucStackBytes--; \
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} while( ucStackBytes ); \
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\
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/* Restore the stack pointer ready to use the restored stack. */ \
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SP = ( uint8_t ) pxRAMStack; \
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}
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/*-----------------------------------------------------------*/
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/*
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* Macro to push the current execution context onto the stack, before the stack
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* is moved to XRAM.
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*/
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#define portSAVE_CONTEXT() \
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{ \
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_asm \
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/* Push ACC first, as when restoring the context it must be restored \
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last (it is used to set the IE register). */ \
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push ACC \
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/* Store the IE register then disable interrupts. */ \
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push IE \
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clr _EA \
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push DPL \
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push DPH \
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push b \
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push ar2 \
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push ar3 \
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push ar4 \
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push ar5 \
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push ar6 \
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push ar7 \
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push ar0 \
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push ar1 \
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push PSW \
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_endasm; \
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PSW = 0; \
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_asm \
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push _bp \
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_endasm; \
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}
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/*-----------------------------------------------------------*/
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/*
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* Macro that restores the execution context from the stack. The execution
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* context was saved into the stack before the stack was copied into XRAM.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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_asm \
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pop _bp \
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pop PSW \
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pop ar1 \
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pop ar0 \
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pop ar7 \
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pop ar6 \
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pop ar5 \
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pop ar4 \
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pop ar3 \
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pop ar2 \
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pop b \
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pop DPH \
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pop DPL \
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/* The next byte of the stack is the IE register. Only the global \
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enable bit forms part of the task context. Pop off the IE then set \
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the global enable bit to match that of the stored IE register. */ \
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pop ACC \
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JB ACC.7,0098$ \
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CLR IE.7 \
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LJMP 0099$ \
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0098$: \
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SETB IE.7 \
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0099$: \
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/* Finally pop off the ACC, which was the first register saved. */ \
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pop ACC \
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reti \
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_endasm; \
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint32_t ulAddress;
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StackType_t *pxStartOfStack;
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/* Leave space to write the size of the stack as the first byte. */
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pxStartOfStack = pxTopOfStack;
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pxTopOfStack++;
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/* Place a few bytes of known values on the bottom of the stack.
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This is just useful for debugging and can be uncommented if required.
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*pxTopOfStack = 0x11;
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pxTopOfStack++;
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*pxTopOfStack = 0x22;
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pxTopOfStack++;
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*pxTopOfStack = 0x33;
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pxTopOfStack++;
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*/
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/* Simulate how the stack would look after a call to the scheduler tick
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ISR.
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The return address that would have been pushed by the MCU. */
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ulAddress = ( uint32_t ) pxCode;
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*pxTopOfStack = ( StackType_t ) ulAddress;
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ulAddress >>= 8;
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pxTopOfStack++;
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*pxTopOfStack = ( StackType_t ) ( ulAddress );
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pxTopOfStack++;
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/* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
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*pxTopOfStack = 0xaa; /* acc */
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pxTopOfStack++;
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/* We want tasks to start with interrupts enabled. */
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*pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
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pxTopOfStack++;
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/* The function parameters will be passed in the DPTR and B register as
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a three byte generic pointer is used. */
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ulAddress = ( uint32_t ) pvParameters;
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*pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
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ulAddress >>= 8;
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*pxTopOfStack++;
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*pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
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ulAddress >>= 8;
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pxTopOfStack++;
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*pxTopOfStack = ( StackType_t ) ulAddress; /* b */
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pxTopOfStack++;
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/* The remaining registers are straight forward. */
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*pxTopOfStack = 0x02; /* R2 */
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pxTopOfStack++;
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*pxTopOfStack = 0x03; /* R3 */
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pxTopOfStack++;
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*pxTopOfStack = 0x04; /* R4 */
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pxTopOfStack++;
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*pxTopOfStack = 0x05; /* R5 */
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pxTopOfStack++;
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*pxTopOfStack = 0x06; /* R6 */
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pxTopOfStack++;
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*pxTopOfStack = 0x07; /* R7 */
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pxTopOfStack++;
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*pxTopOfStack = 0x00; /* R0 */
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pxTopOfStack++;
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*pxTopOfStack = 0x01; /* R1 */
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pxTopOfStack++;
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*pxTopOfStack = 0x00; /* PSW */
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pxTopOfStack++;
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*pxTopOfStack = 0xbb; /* BP */
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/* Dont increment the stack size here as we don't want to include
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the stack size byte as part of the stack size count.
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Finally we place the stack size at the beginning. */
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*pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
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/* Unlike most ports, we return the start of the stack as this is where the
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size of the stack is stored. */
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return pxStartOfStack;
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Setup timer 2 to generate the RTOS tick. */
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prvSetupTimerInterrupt();
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/* Make sure we start with the expected SFR page. This line should not
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really be required. */
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SFRPAGE = 0;
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/* Copy the stack for the first task to execute from XRAM into the stack,
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restore the task context from the new stack, then start running the task. */
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portCOPY_XRAM_TO_STACK();
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portRESTORE_CONTEXT();
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/* Should never get here! */
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return pdTRUE;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented for this port. */
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}
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/*-----------------------------------------------------------*/
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/*
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* Manual context switch. The first thing we do is save the registers so we
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* can use a naked attribute.
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*/
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void vPortYield( void ) _naked
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{
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/* Save the execution context onto the stack, then copy the entire stack
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to XRAM. This is necessary as the internal RAM is only large enough to
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hold one stack, and we want one per task.
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PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
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IS REQUIRED. */
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portSAVE_CONTEXT();
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portCOPY_STACK_TO_XRAM();
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/* Call the standard scheduler context switch function. */
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vTaskSwitchContext();
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/* Copy the stack of the task about to execute from XRAM into RAM and
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restore it's context ready to run on exiting. */
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portCOPY_XRAM_TO_STACK();
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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#if configUSE_PREEMPTION == 1
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void vTimer2ISR( void ) interrupt 5 _naked
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{
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/* Preemptive context switch function triggered by the timer 2 ISR.
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This does the same as vPortYield() (see above) with the addition
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of incrementing the RTOS tick count. */
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portSAVE_CONTEXT();
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portCOPY_STACK_TO_XRAM();
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if( xTaskIncrementTick() != pdFALSE )
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{
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vTaskSwitchContext();
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}
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portCLEAR_INTERRUPT_FLAG();
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portCOPY_XRAM_TO_STACK();
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portRESTORE_CONTEXT();
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}
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#else
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void vTimer2ISR( void ) interrupt 5
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{
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/* When using the cooperative scheduler the timer 2 ISR is only
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required to increment the RTOS tick count. */
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xTaskIncrementTick();
|
||
|
|
portCLEAR_INTERRUPT_FLAG();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvSetupTimerInterrupt( void )
|
||
|
|
{
|
||
|
|
uint8_t ucOriginalSFRPage;
|
||
|
|
|
||
|
|
/* Constants calculated to give the required timer capture values. */
|
||
|
|
const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
|
||
|
|
const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
|
||
|
|
const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
|
||
|
|
const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
|
||
|
|
const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
|
||
|
|
|
||
|
|
/* NOTE: This uses a timer only present on 8052 architecture. */
|
||
|
|
|
||
|
|
/* Remember the current SFR page so we can restore it at the end of the
|
||
|
|
function. */
|
||
|
|
ucOriginalSFRPage = SFRPAGE;
|
||
|
|
SFRPAGE = 0;
|
||
|
|
|
||
|
|
/* TMR2CF can be left in its default state. */
|
||
|
|
TMR2CF = ( uint8_t ) 0;
|
||
|
|
|
||
|
|
/* Setup the overflow reload value. */
|
||
|
|
RCAP2L = ucLowCaptureByte;
|
||
|
|
RCAP2H = ucHighCaptureByte;
|
||
|
|
|
||
|
|
/* The initial load is performed manually. */
|
||
|
|
TMR2L = ucLowCaptureByte;
|
||
|
|
TMR2H = ucHighCaptureByte;
|
||
|
|
|
||
|
|
/* Enable the timer 2 interrupts. */
|
||
|
|
IE |= portTIMER_2_INTERRUPT_ENABLE;
|
||
|
|
|
||
|
|
/* Interrupts are disabled when this is called so the timer can be started
|
||
|
|
here. */
|
||
|
|
TMR2CN = portENABLE_TIMER;
|
||
|
|
|
||
|
|
/* Restore the original SFR page. */
|
||
|
|
SFRPAGE = ucOriginalSFRPage;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|