517 lines
17 KiB
C
517 lines
17 KiB
C
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the SH2A port.
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*----------------------------------------------------------*/
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/* Standard C includes. */
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#include "limits.h"
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Library includes. */
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#include "string.h"
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/* Hardware specifics. */
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#include "machine.h"
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/*-----------------------------------------------------------*/
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/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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PSW is set with U and I set, and PM and IPL clear. */
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#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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/* The peripheral clock is divided by this value before being supplying the
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CMT. */
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#if ( configUSE_TICKLESS_IDLE == 0 )
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/* If tickless idle is not used then the divisor can be fixed. */
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#define portCLOCK_DIVISOR 8UL
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#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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#define portCLOCK_DIVISOR 512UL
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#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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#define portCLOCK_DIVISOR 128UL
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#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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#define portCLOCK_DIVISOR 32UL
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#else
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#define portCLOCK_DIVISOR 8UL
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#endif
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/* Keys required to lock and unlock access to certain system registers
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respectively. */
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#define portUNLOCK_KEY 0xA50B
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#define portLOCK_KEY 0xA500
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/*-----------------------------------------------------------*/
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/*
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* Function to start the first task executing - written in asm code as direct
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* access to registers is required.
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*/
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extern void prvStartFirstTask( void );
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/*
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* The tick ISR handler. The peripheral used is configured by the application
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* via a hook/callback function.
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*/
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__interrupt static void prvTickISR( void );
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/*
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* Sets up the periodic ISR used for the RTOS tick using the CMT.
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* The application writer can define configSETUP_TICK_INTERRUPT() (in
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* FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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* in place of prvSetupTimerInterrupt().
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*/
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static void prvSetupTimerInterrupt( void );
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#ifndef configSETUP_TICK_INTERRUPT
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/* The user has not provided their own tick interrupt configuration so use
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the definition in this file (which uses the interval timer). */
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#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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#endif /* configSETUP_TICK_INTERRUPT */
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/*
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* Called after the sleep mode registers have been configured, prvSleep()
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* executes the pre and post sleep macros, and actually calls the wait
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* instruction.
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*/
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#if configUSE_TICKLESS_IDLE == 1
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static void prvSleep( TickType_t xExpectedIdleTime );
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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extern void *pxCurrentTCB;
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/*-----------------------------------------------------------*/
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/* Calculate how many clock increments make up a single tick period. */
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static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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#if configUSE_TICKLESS_IDLE == 1
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/* Holds the maximum number of ticks that can be suppressed - which is
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basically how far into the future an interrupt can be generated. Set
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during initialisation. This is the maximum possible value that the
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compare match register can hold divided by ulMatchValueForOneTick. */
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static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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/* Flag set from the tick interrupt to allow the sleep processing to know if
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sleep mode was exited because of a tick interrupt, or an interrupt
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generated by something else. */
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static volatile uint32_t ulTickFlag = pdFALSE;
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/* The CMT counter is stopped temporarily each time it is re-programmed.
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The following constant offsets the CMT counter match value by the number of
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CMT counts that would typically be missed while the counter was stopped to
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compensate for the lost time. The large difference between the divided CMT
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clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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equal zero - and be optimised away. */
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static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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#endif
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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/* Offset to end up on 8 byte boundary. */
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pxTopOfStack--;
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/* R0 is not included as it is the stack pointer. */
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*pxTopOfStack = 0x00;
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pxTopOfStack--;
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*pxTopOfStack = 0x00;
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_PSW;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode;
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/* When debugging it can be useful if every register is set to a known
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value. Otherwise code space can be saved by just setting the registers
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that need to be set. */
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#ifdef USE_FULL_REGISTER_INITIALISATION
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{
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pxTopOfStack--;
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*pxTopOfStack = 0x12345678; /* r15. */
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pxTopOfStack--;
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*pxTopOfStack = 0xaaaabbbb;
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pxTopOfStack--;
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*pxTopOfStack = 0xdddddddd;
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pxTopOfStack--;
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*pxTopOfStack = 0xcccccccc;
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pxTopOfStack--;
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*pxTopOfStack = 0xbbbbbbbb;
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pxTopOfStack--;
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*pxTopOfStack = 0xaaaaaaaa;
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pxTopOfStack--;
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*pxTopOfStack = 0x99999999;
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pxTopOfStack--;
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*pxTopOfStack = 0x88888888;
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pxTopOfStack--;
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*pxTopOfStack = 0x77777777;
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pxTopOfStack--;
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*pxTopOfStack = 0x66666666;
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pxTopOfStack--;
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*pxTopOfStack = 0x55555555;
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pxTopOfStack--;
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*pxTopOfStack = 0x44444444;
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pxTopOfStack--;
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*pxTopOfStack = 0x33333333;
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pxTopOfStack--;
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*pxTopOfStack = 0x22222222;
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pxTopOfStack--;
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}
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#else
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{
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/* Leave space for the registers that will get popped from the stack
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when the task first starts executing. */
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pxTopOfStack -= 15;
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}
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#endif
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = 0x12345678; /* Accumulator. */
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pxTopOfStack--;
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*pxTopOfStack = 0x87654321; /* Accumulator. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Use pxCurrentTCB just so it does not get optimised away. */
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if( pxCurrentTCB != NULL )
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{
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/* Call an application function to set up the timer that will generate
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the tick interrupt. This way the application can decide which
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peripheral to use. If tickless mode is used then the default
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implementation defined in this file (which uses CMT0) should not be
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overridden. */
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configSETUP_TICK_INTERRUPT();
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/* Enable the software interrupt. */
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_IEN( _ICU_SWINT ) = 1;
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/* Ensure the software interrupt is clear. */
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_IR( _ICU_SWINT ) = 0;
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/* Ensure the software interrupt is set to the kernel priority. */
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_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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/* Start the first task. */
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prvStartFirstTask();
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}
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/* Execution should not reach here as the tasks are now running!
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prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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a warning about a statically declared function not being referenced in the
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case that the application writer has provided their own tick interrupt
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configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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their own routine will be called in place of prvSetupTimerInterrupt()). */
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prvSetupTimerInterrupt();
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/* Should not get here. */
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return pdFAIL;
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}
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/*-----------------------------------------------------------*/
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#pragma vector = configTICK_VECTOR
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__interrupt static void prvTickISR( void )
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{
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/* Re-enable interrupts. */
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__enable_interrupt();
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/* Increment the tick, and perform any processing the new tick value
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necessitates. */
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__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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{
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if( xTaskIncrementTick() != pdFALSE )
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{
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taskYIELD();
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}
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}
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__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
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#if configUSE_TICKLESS_IDLE == 1
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{
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/* The CPU woke because of a tick. */
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ulTickFlag = pdTRUE;
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/* If this is the first tick since exiting tickless mode then the CMT
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compare match value needs resetting. */
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CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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}
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#endif
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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Artificially force an assert. */
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configASSERT( pxCurrentTCB == NULL );
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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/* Unlock. */
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SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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/* Enable CMT0. */
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MSTP( CMT0 ) = 0;
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/* Lock again. */
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SYSTEM.PRCR.WORD = portLOCK_KEY;
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/* Interrupt on compare match. */
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CMT0.CMCR.BIT.CMIE = 1;
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/* Set the compare match value. */
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CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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/* Divide the PCLK. */
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#if portCLOCK_DIVISOR == 512
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{
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CMT0.CMCR.BIT.CKS = 3;
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}
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#elif portCLOCK_DIVISOR == 128
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{
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CMT0.CMCR.BIT.CKS = 2;
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}
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#elif portCLOCK_DIVISOR == 32
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{
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CMT0.CMCR.BIT.CKS = 1;
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}
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#elif portCLOCK_DIVISOR == 8
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{
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CMT0.CMCR.BIT.CKS = 0;
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}
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#else
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{
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#error Invalid portCLOCK_DIVISOR setting
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}
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#endif
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/* Enable the interrupt... */
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_IEN( _CMT0_CMI0 ) = 1;
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/* ...and set its priority to the application defined kernel priority. */
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_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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/* Start the timer. */
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CMT.CMSTR0.BIT.STR0 = 1;
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}
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/*-----------------------------------------------------------*/
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#if configUSE_TICKLESS_IDLE == 1
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static void prvSleep( TickType_t xExpectedIdleTime )
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{
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/* Allow the application to define some pre-sleep processing. */
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configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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means the application defined code has already executed the WAIT
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instruction. */
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if( xExpectedIdleTime > 0 )
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{
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__wait_for_interrupt();
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}
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/* Allow the application to define some post sleep processing. */
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configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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}
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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#if configUSE_TICKLESS_IDLE == 1
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void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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{
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uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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eSleepModeStatus eSleepAction;
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/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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/* Make sure the CMT reload value does not overflow the counter. */
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if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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{
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xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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}
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/* Calculate the reload value required to wait xExpectedIdleTime tick
|
||
|
|
periods. */
|
||
|
|
ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
|
||
|
|
if( ulMatchValue > ulStoppedTimerCompensation )
|
||
|
|
{
|
||
|
|
/* Compensate for the fact that the CMT is going to be stopped
|
||
|
|
momentarily. */
|
||
|
|
ulMatchValue -= ulStoppedTimerCompensation;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Stop the CMT momentarily. The time the CMT is stopped for is
|
||
|
|
accounted for as best it can be, but using the tickless mode will
|
||
|
|
inevitably result in some tiny drift of the time maintained by the
|
||
|
|
kernel with respect to calendar time. */
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 0;
|
||
|
|
while( CMT.CMSTR0.BIT.STR0 == 1 )
|
||
|
|
{
|
||
|
|
/* Nothing to do here. */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Critical section using the global interrupt bit as the i bit is
|
||
|
|
automatically reset by the WAIT instruction. */
|
||
|
|
__disable_interrupt();
|
||
|
|
|
||
|
|
/* The tick flag is set to false before sleeping. If it is true when
|
||
|
|
sleep mode is exited then sleep mode was probably exited because the
|
||
|
|
tick was suppressed for the entire xExpectedIdleTime period. */
|
||
|
|
ulTickFlag = pdFALSE;
|
||
|
|
|
||
|
|
/* If a context switch is pending then abandon the low power entry as
|
||
|
|
the context switch might have been pended by an external interrupt that
|
||
|
|
requires processing. */
|
||
|
|
eSleepAction = eTaskConfirmSleepModeStatus();
|
||
|
|
if( eSleepAction == eAbortSleep )
|
||
|
|
{
|
||
|
|
/* Restart tick. */
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 1;
|
||
|
|
__enable_interrupt();
|
||
|
|
}
|
||
|
|
else if( eSleepAction == eNoTasksWaitingTimeout )
|
||
|
|
{
|
||
|
|
/* Protection off. */
|
||
|
|
SYSTEM.PRCR.WORD = portUNLOCK_KEY;
|
||
|
|
|
||
|
|
/* Ready for software standby with all clocks stopped. */
|
||
|
|
SYSTEM.SBYCR.BIT.SSBY = 1;
|
||
|
|
|
||
|
|
/* Protection on. */
|
||
|
|
SYSTEM.PRCR.WORD = portLOCK_KEY;
|
||
|
|
|
||
|
|
/* Sleep until something happens. Calling prvSleep() will
|
||
|
|
automatically reset the i bit in the PSW. */
|
||
|
|
prvSleep( xExpectedIdleTime );
|
||
|
|
|
||
|
|
/* Restart the CMT. */
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 1;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Protection off. */
|
||
|
|
SYSTEM.PRCR.WORD = portUNLOCK_KEY;
|
||
|
|
|
||
|
|
/* Ready for deep sleep mode. */
|
||
|
|
SYSTEM.MSTPCRC.BIT.DSLPE = 1;
|
||
|
|
SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
|
||
|
|
SYSTEM.SBYCR.BIT.SSBY = 0;
|
||
|
|
|
||
|
|
/* Protection on. */
|
||
|
|
SYSTEM.PRCR.WORD = portLOCK_KEY;
|
||
|
|
|
||
|
|
/* Adjust the match value to take into account that the current
|
||
|
|
time slice is already partially complete. */
|
||
|
|
ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
|
||
|
|
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
|
||
|
|
|
||
|
|
/* Restart the CMT to count up to the new match value. */
|
||
|
|
CMT0.CMCNT = 0;
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 1;
|
||
|
|
|
||
|
|
/* Sleep until something happens. Calling prvSleep() will
|
||
|
|
automatically reset the i bit in the PSW. */
|
||
|
|
prvSleep( xExpectedIdleTime );
|
||
|
|
|
||
|
|
/* Stop CMT. Again, the time the SysTick is stopped for is
|
||
|
|
accounted for as best it can be, but using the tickless mode will
|
||
|
|
inevitably result in some tiny drift of the time maintained by the
|
||
|
|
kernel with respect to calendar time. */
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 0;
|
||
|
|
while( CMT.CMSTR0.BIT.STR0 == 1 )
|
||
|
|
{
|
||
|
|
/* Nothing to do here. */
|
||
|
|
}
|
||
|
|
|
||
|
|
ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
|
||
|
|
|
||
|
|
if( ulTickFlag != pdFALSE )
|
||
|
|
{
|
||
|
|
/* The tick interrupt has already executed, although because
|
||
|
|
this function is called with the scheduler suspended the actual
|
||
|
|
tick processing will not occur until after this function has
|
||
|
|
exited. Reset the match value with whatever remains of this
|
||
|
|
tick period. */
|
||
|
|
ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
|
||
|
|
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
|
||
|
|
|
||
|
|
/* The tick interrupt handler will already have pended the tick
|
||
|
|
processing in the kernel. As the pending tick will be
|
||
|
|
processed as soon as this function exits, the tick value
|
||
|
|
maintained by the tick is stepped forward by one less than the
|
||
|
|
time spent sleeping. The actual stepping of the tick appears
|
||
|
|
later in this function. */
|
||
|
|
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Something other than the tick interrupt ended the sleep.
|
||
|
|
How many complete tick periods passed while the processor was
|
||
|
|
sleeping? */
|
||
|
|
ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
|
||
|
|
|
||
|
|
/* The match value is set to whatever fraction of a single tick
|
||
|
|
period remains. */
|
||
|
|
ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
|
||
|
|
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restart the CMT so it runs up to the match value. The match value
|
||
|
|
will get set to the value required to generate exactly one tick period
|
||
|
|
the next time the CMT interrupt executes. */
|
||
|
|
CMT0.CMCNT = 0;
|
||
|
|
CMT.CMSTR0.BIT.STR0 = 1;
|
||
|
|
|
||
|
|
/* Wind the tick forward by the number of tick periods that the CPU
|
||
|
|
remained in a low power state. */
|
||
|
|
vTaskStepTick( ulCompleteTickPeriods );
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
||
|
|
|