616 lines
21 KiB
C
616 lines
21 KiB
C
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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Changes between V1.2.4 and V1.2.5
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+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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interrupt flag setting. Using the two bits defined within
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portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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before the test was performed.
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Changes from V1.2.5
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+ Set the interrupt vector address to 0x08. Previously it was at the
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incorrect address for compatibility mode of 0x18.
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Changes from V2.1.1
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+ PCLATU and PCLATH are now saved as part of the context. This allows
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function pointers to be used within tasks. Thanks to Javier Espeche
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for the enhancement.
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Changes from V2.3.1
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+ TABLAT is now saved as part of the task context.
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Changes from V3.2.0
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+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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value and does not write to the register.
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*/
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* MPLAB library include file. */
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#include "timers.h"
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PIC port.
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*----------------------------------------------------------*/
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/* Hardware setup for tick. */
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#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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/* Initial interrupt enable state for newly created tasks. This value is
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copied into INTCON when a task switches in for the first time. */
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#define portINITAL_INTERRUPT_STATE 0xc0
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/* Just the bit within INTCON for the global interrupt flag. */
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#define portGLOBAL_INTERRUPT_FLAG 0x80
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/* Constant used for context switch macro when we require the interrupt
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enable state to be unchanged when the interrupted task is switched back in. */
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#define portINTERRUPTS_UNCHANGED 0x00
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/* Some memory areas get saved as part of the task context. These memory
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area's get used by the compiler for temporary storage, especially when
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performing mathematical operations, or when using 32bit data types. This
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constant defines the size of memory area which must be saved. */
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#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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/* We require the address of the pxCurrentTCB variable, but don't want to know
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any details of its type. */
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typedef void TCB_t;
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extern volatile TCB_t * volatile pxCurrentTCB;
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/* IO port constants. */
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#define portBIT_SET ( ( uint8_t ) 1 )
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#define portBIT_CLEAR ( ( uint8_t ) 0 )
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/*
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* The serial port ISR's are defined in serial.c, but are called from portable
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* as they use the same vector as the tick ISR.
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*/
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void vSerialTxISR( void );
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void vSerialRxISR( void );
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/*
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* Perform hardware setup to enable ticks.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* ISR to maintain the tick, and perform tick context switches if the
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* preemptive scheduler is being used.
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*/
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static void prvTickISR( void );
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/*
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* ISR placed on the low priority vector. This calls the appropriate ISR for
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* the actual interrupt.
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*/
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static void prvLowInterrupt( void );
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/*
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* Macro that pushes all the registers that make up the context of a task onto
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* the stack, then saves the new top of stack into the TCB.
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*
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* If this is called from an ISR then the interrupt enable bits must have been
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* set for the ISR to ever get called. Therefore we want to save the INTCON
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* register with the enable bits forced to be set - and ucForcedInterruptFlags
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* must contain these bit settings. This means the interrupts will again be
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* enabled when the interrupted task is switched back in.
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*
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* If this is called from a manual context switch (i.e. from a call to yield),
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* then we want to save the INTCON so it is restored with its current state,
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* and ucForcedInterruptFlags must be 0. This allows a yield from within
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* a critical section.
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*
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* The compiler uses some locations at the bottom of the memory for temporary
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* storage during math and other computations. This is especially true if
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* 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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* and MATH_DATA sections have to be stored in there entirety as part of a task
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* context. This macro stores from data address 0x00 to
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* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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* applications but you should check the map file for your project to ensure
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* this is sufficient for your needs. It is not clear whether this size is
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* fixed for all compilations or has the potential to be program specific.
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*/
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#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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{ \
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_asm \
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/* Save the status and WREG registers first, as these will get modified \
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by the operations below. */ \
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MOVFF WREG, PREINC1 \
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MOVFF STATUS, PREINC1 \
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/* Save the INTCON register with the appropriate bits forced if \
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necessary - as described above. */ \
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MOVFF INTCON, WREG \
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IORLW ucForcedInterruptFlags \
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MOVFF WREG, PREINC1 \
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_endasm \
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\
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portDISABLE_INTERRUPTS(); \
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\
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_asm \
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/* Store the necessary registers to the stack. */ \
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MOVFF BSR, PREINC1 \
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MOVFF FSR2L, PREINC1 \
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MOVFF FSR2H, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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MOVFF TABLAT, PREINC1 \
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MOVFF TBLPTRU, PREINC1 \
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MOVFF TBLPTRH, PREINC1 \
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MOVFF TBLPTRL, PREINC1 \
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MOVFF PRODH, PREINC1 \
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MOVFF PRODL, PREINC1 \
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MOVFF PCLATU, PREINC1 \
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MOVFF PCLATH, PREINC1 \
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/* Store the .tempdata and MATH_DATA areas as described above. */ \
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CLRF FSR0L, 0 \
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CLRF FSR0H, 0 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF INDF0, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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/* Store the hardware stack pointer in a temp register before we \
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modify it. */ \
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MOVFF STKPTR, FSR0L \
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_endasm \
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\
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/* Store each address from the hardware stack. */ \
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while( STKPTR > ( uint8_t ) 0 ) \
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{ \
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_asm \
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MOVFF TOSL, PREINC1 \
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MOVFF TOSH, PREINC1 \
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MOVFF TOSU, PREINC1 \
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POP \
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_endasm \
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} \
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\
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_asm \
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/* Store the number of addresses on the hardware stack (from the \
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temporary register). */ \
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MOVFF FSR0L, PREINC1 \
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MOVF PREINC1, 1, 0 \
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_endasm \
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\
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/* Save the new top of the software stack in the TCB. */ \
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_asm \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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MOVFF FSR1L, POSTINC0 \
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MOVFF FSR1H, POSTINC0 \
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_endasm \
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}
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/*-----------------------------------------------------------*/
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/*
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* This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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* details.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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_asm \
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/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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\
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/* De-reference FSR0 to set the address it holds into FSR1. \
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(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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MOVFF POSTINC0, FSR1L \
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MOVFF POSTINC0, FSR1H \
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\
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/* How many return addresses are there on the hardware stack? Discard \
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the first byte as we are pointing to the next free space. */ \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, FSR0L \
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_endasm \
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\
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/* Fill the hardware stack from our software stack. */ \
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STKPTR = 0; \
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\
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while( STKPTR < FSR0L ) \
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{ \
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_asm \
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PUSH \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSU, 0 \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSH, 0 \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSL, 0 \
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_endasm \
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} \
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\
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_asm \
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/* Restore the .tmpdata and MATH_DATA memory. */ \
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MOVFF POSTDEC1, FSR0H \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, INDF0 \
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/* Restore the other registers forming the tasks context. */ \
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MOVFF POSTDEC1, PCLATH \
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MOVFF POSTDEC1, PCLATU \
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MOVFF POSTDEC1, PRODL \
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MOVFF POSTDEC1, PRODH \
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MOVFF POSTDEC1, TBLPTRL \
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MOVFF POSTDEC1, TBLPTRH \
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MOVFF POSTDEC1, TBLPTRU \
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MOVFF POSTDEC1, TABLAT \
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MOVFF POSTDEC1, FSR0H \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, FSR2H \
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MOVFF POSTDEC1, FSR2L \
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MOVFF POSTDEC1, BSR \
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/* The next byte is the INTCON register. Read this into WREG as some \
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manipulation is required. */ \
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MOVFF POSTDEC1, WREG \
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_endasm \
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\
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/* From the INTCON register, only the interrupt enable bits form part \
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of the tasks context. It is perfectly legitimate for another task to \
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have modified any other bits. We therefore only restore the top two bits. \
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*/ \
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if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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{ \
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_asm \
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MOVFF POSTDEC1, STATUS \
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MOVFF POSTDEC1, WREG \
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/* Return enabling interrupts. */ \
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RETFIE 0 \
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_endasm \
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} \
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else \
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{ \
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_asm \
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MOVFF POSTDEC1, STATUS \
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MOVFF POSTDEC1, WREG \
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/* Return without effecting interrupts. The context may have \
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been saved from a critical region. */ \
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RETURN 0 \
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_endasm \
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} \
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint32_t ulAddress;
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uint8_t ucBlock;
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/* Place a few bytes of known values on the bottom of the stack.
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This is just useful for debugging. */
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*pxTopOfStack = 0x11;
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pxTopOfStack++;
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*pxTopOfStack = 0x22;
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pxTopOfStack++;
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*pxTopOfStack = 0x33;
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pxTopOfStack++;
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/* Simulate how the stack would look after a call to vPortYield() generated
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by the compiler.
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|
||
|
|
First store the function parameters. This is where the task will expect to
|
||
|
|
find them when it starts running. */
|
||
|
|
ulAddress = ( uint32_t ) pvParameters;
|
||
|
|
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
ulAddress >>= 8;
|
||
|
|
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* Next we just leave a space. When a context is saved the stack pointer
|
||
|
|
is incremented before it is used so as not to corrupt whatever the stack
|
||
|
|
pointer is actually pointing to. This is especially necessary during
|
||
|
|
function epilogue code generated by the compiler. */
|
||
|
|
*pxTopOfStack = 0x44;
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* Next are all the registers that form part of the task context. */
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* INTCON is saved with interrupts enabled. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* Next the .tmpdata and MATH_DATA sections. */
|
||
|
|
for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
|
||
|
|
{
|
||
|
|
*pxTopOfStack = ( StackType_t ) ucBlock;
|
||
|
|
*pxTopOfStack++;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Store the top of the global data section. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* The only function return address so far is the address of the
|
||
|
|
task. */
|
||
|
|
ulAddress = ( uint32_t ) pxCode;
|
||
|
|
|
||
|
|
/* TOS low. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||
|
|
pxTopOfStack++;
|
||
|
|
ulAddress >>= 8;
|
||
|
|
|
||
|
|
/* TOS high. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||
|
|
pxTopOfStack++;
|
||
|
|
ulAddress >>= 8;
|
||
|
|
|
||
|
|
/* TOS even higher. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
/* Store the number of return addresses on the hardware stack - so far only
|
||
|
|
the address of the task entry point. */
|
||
|
|
*pxTopOfStack = ( StackType_t ) 1;
|
||
|
|
pxTopOfStack++;
|
||
|
|
|
||
|
|
return pxTopOfStack;
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xPortStartScheduler( void )
|
||
|
|
{
|
||
|
|
/* Setup a timer for the tick ISR is using the preemptive scheduler. */
|
||
|
|
prvSetupTimerInterrupt();
|
||
|
|
|
||
|
|
/* Restore the context of the first task to run. */
|
||
|
|
portRESTORE_CONTEXT();
|
||
|
|
|
||
|
|
/* Should not get here. Use the function name to stop compiler warnings. */
|
||
|
|
( void ) prvLowInterrupt;
|
||
|
|
( void ) prvTickISR;
|
||
|
|
|
||
|
|
return pdTRUE;
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortEndScheduler( void )
|
||
|
|
{
|
||
|
|
/* It is unlikely that the scheduler for the PIC port will get stopped
|
||
|
|
once running. If required disable the tick interrupt here, then return
|
||
|
|
to xPortStartScheduler(). */
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Manual context switch. This is similar to the tick context switch,
|
||
|
|
* but does not increment the tick count. It must be identical to the
|
||
|
|
* tick context switch in how it stores the stack of a task.
|
||
|
|
*/
|
||
|
|
void vPortYield( void )
|
||
|
|
{
|
||
|
|
/* This can get called with interrupts either enabled or disabled. We
|
||
|
|
will save the INTCON register with the interrupt enable bits unmodified. */
|
||
|
|
portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
|
||
|
|
|
||
|
|
/* Switch to the highest priority task that is ready to run. */
|
||
|
|
vTaskSwitchContext();
|
||
|
|
|
||
|
|
/* Start executing the task we have just switched to. */
|
||
|
|
portRESTORE_CONTEXT();
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Vector for ISR. Nothing here must alter any registers!
|
||
|
|
*/
|
||
|
|
#pragma code high_vector=0x08
|
||
|
|
static void prvLowInterrupt( void )
|
||
|
|
{
|
||
|
|
/* Was the interrupt the tick? */
|
||
|
|
if( PIR1bits.CCP1IF )
|
||
|
|
{
|
||
|
|
_asm
|
||
|
|
goto prvTickISR
|
||
|
|
_endasm
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Was the interrupt a byte being received? */
|
||
|
|
if( PIR1bits.RCIF )
|
||
|
|
{
|
||
|
|
_asm
|
||
|
|
goto vSerialRxISR
|
||
|
|
_endasm
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Was the interrupt the Tx register becoming empty? */
|
||
|
|
if( PIR1bits.TXIF )
|
||
|
|
{
|
||
|
|
if( PIE1bits.TXIE )
|
||
|
|
{
|
||
|
|
_asm
|
||
|
|
goto vSerialTxISR
|
||
|
|
_endasm
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#pragma code
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ISR for the tick.
|
||
|
|
* This increments the tick count and, if using the preemptive scheduler,
|
||
|
|
* performs a context switch. This must be identical to the manual
|
||
|
|
* context switch in how it stores the context of a task.
|
||
|
|
*/
|
||
|
|
static void prvTickISR( void )
|
||
|
|
{
|
||
|
|
/* Interrupts must have been enabled for the ISR to fire, so we have to
|
||
|
|
save the context with interrupts enabled. */
|
||
|
|
portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
|
||
|
|
PIR1bits.CCP1IF = 0;
|
||
|
|
|
||
|
|
/* Maintain the tick count. */
|
||
|
|
if( xTaskIncrementTick() != pdFALSE )
|
||
|
|
{
|
||
|
|
/* Switch to the highest priority task that is ready to run. */
|
||
|
|
vTaskSwitchContext();
|
||
|
|
}
|
||
|
|
|
||
|
|
portRESTORE_CONTEXT();
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Setup a timer for a regular tick.
|
||
|
|
*/
|
||
|
|
static void prvSetupTimerInterrupt( void )
|
||
|
|
{
|
||
|
|
const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
|
||
|
|
uint32_t ulCompareValue;
|
||
|
|
uint8_t ucByte;
|
||
|
|
|
||
|
|
/* Interrupts are disabled when this function is called.
|
||
|
|
|
||
|
|
Setup CCP1 to provide the tick interrupt using a compare match on timer
|
||
|
|
1.
|
||
|
|
|
||
|
|
Clear the time count then setup timer. */
|
||
|
|
TMR1H = ( uint8_t ) 0x00;
|
||
|
|
TMR1L = ( uint8_t ) 0x00;
|
||
|
|
|
||
|
|
/* Set the compare match value. */
|
||
|
|
ulCompareValue = ulConstCompareValue;
|
||
|
|
CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||
|
|
ulCompareValue >>= ( uint32_t ) 8;
|
||
|
|
CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||
|
|
|
||
|
|
CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
|
||
|
|
CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
|
||
|
|
CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
|
||
|
|
CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
|
||
|
|
PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
|
||
|
|
|
||
|
|
/* We are only going to use the global interrupt bit, so set the peripheral
|
||
|
|
bit to true. */
|
||
|
|
INTCONbits.GIEL = portBIT_SET;
|
||
|
|
|
||
|
|
/* Provided library function for setting up the timer that will produce the
|
||
|
|
tick. */
|
||
|
|
OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
|
||
|
|
}
|
||
|
|
|