77 lines
3.4 KiB
ArmAsm
77 lines
3.4 KiB
ArmAsm
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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PUBLIC SecureContext_LoadContextAsm
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PUBLIC SecureContext_SaveContextAsm
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#if ( configENABLE_FPU == 1 )
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#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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#endif
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/*-----------------------------------------------------------*/
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SecureContext_LoadContextAsm:
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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#if ( configENABLE_MPU == 1 )
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ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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msr control, r3 /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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msr psplim, r2 /* PSPLIM = r2. */
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msr psp, r1 /* PSP = r1. */
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load_ctx_therad_mode:
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bx lr
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/*-----------------------------------------------------------*/
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SecureContext_SaveContextAsm:
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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mrs r1, psp /* r1 = PSP. */
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#if ( configENABLE_MPU == 1 )
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mrs r2, control /* r2 = CONTROL. */
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subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
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str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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stmia r1!, {r2} /* Store CONTROL value on the stack. */
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#else /* configENABLE_MPU */
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str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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#endif /* configENABLE_MPU */
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movs r1, #0 /* r1 = securecontextNO_STACK. */
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msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
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msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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save_ctx_therad_mode:
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bx lr
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/*-----------------------------------------------------------*/
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END
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