131 lines
4.2 KiB
Plaintext
131 lines
4.2 KiB
Plaintext
package com.minres.coredsl.json.tests
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import com.google.inject.Inject
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import com.minres.coredsl.coreDsl.DescriptionContent
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import org.eclipse.emf.ecore.util.EcoreUtil
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import org.eclipse.xtext.generator.GeneratorContext
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import org.eclipse.xtext.generator.IGenerator2
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import org.eclipse.xtext.generator.InMemoryFileSystemAccess
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import org.eclipse.xtext.testing.InjectWith
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import org.eclipse.xtext.testing.XtextRunner
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import org.eclipse.xtext.testing.util.ParseHelper
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import org.eclipse.xtext.util.CancelIndicator
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import org.junit.Test
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import org.junit.runner.RunWith
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import static org.junit.Assert.*
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import static extension com.google.common.io.CharStreams.*
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import com.minres.coredsl.coreDsl.InstructionSet
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import java.io.FileReader
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import org.eclipse.xtext.testing.validation.ValidationTestHelper
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@RunWith(XtextRunner)
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@InjectWith(CoreDslInjectorProvider)
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class CoreDslGenerationTest{
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@Inject IGenerator2 generator
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@Inject extension ParseHelper<DescriptionContent> parseHelper
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@Inject ValidationTestHelper validator
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val isa_rv32i = '''
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Core RV32I {
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architectural_state {
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unsigned int XLEN, FLEN;
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unsigned CSR_SIZE = 4096;
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unsigned REG_FILE_SIZE=32;
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register unsigned<XLEN> PC [[is_pc]];
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register unsigned<XLEN> X[REG_FILE_SIZE];
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extern char MEM[1<<XLEN];
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extern unsigned CSR[CSR_SIZE];
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}
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instructions [[hls]] {
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ADDI {
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encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] + imm;
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}
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}
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SLTI {
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encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] < imm? 1 : 0;
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}
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}
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SLTIU {
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encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] < imm? 1 : 0;
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}
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}
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SW {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
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assembly:"{name(rs2)}, {imm}({name(rs1)})";
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behavior: {
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int offset = X[rs1] + imm;
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MEM[offset] = X[rs2];
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}
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}
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JAL[[no_cont]] {
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encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
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behavior: {
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if(rd!=0) X[rd] = (unsigned)PC;
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PC = PC+imm;
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}
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}
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}
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}
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'''
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@Test
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def void loadSimpleModel() {
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val content = new FileReader('inputs/isa_1.core_desc').readLines.join('\n').parse
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validator.assertNoErrors(content)
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val InstructionSet result = content.definitions.get(0) as InstructionSet
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assertNotNull(result)
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assertEquals("RV32I", result.name)
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assertNull(result.superType)
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assertEquals(9, result.archStateBody.size())
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assertNotNull(result.instructions)
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assertEquals(5, result.instructions.size)
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val i0 = result.instructions.get(0);
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assertEquals("ADDI", i0.name)
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assertEquals(5, i0.encoding.fields.size)
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val i1 = result.instructions.get(1);
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assertEquals("SLTI", i1.name)
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assertEquals(5, i1.encoding.fields.size)
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val i2 = result.instructions.get(2);
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assertEquals("SLTIU", i2.name)
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assertEquals(5, i2.encoding.fields.size)
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val i3 = result.instructions.get(3);
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assertEquals("SW", i3.name)
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assertEquals(6, i3.encoding.fields.size)
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}
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@Test
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def void generateCpp() {
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val content = parseHelper.parse(isa_rv32i)
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assertNotNull(content)
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assertEquals(1, content.definitions.size)
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val resource = content.eResource
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EcoreUtil.resolveAll(resource);
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validator.assertNoErrors(content)
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assertEquals(0, resource.errors.size)
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assertEquals(0, resource.warnings.size)
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val fsa = new InMemoryFileSystemAccess()
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generator.doGenerate(content.eResource, fsa, new GeneratorContext => [
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cancelIndicator = CancelIndicator.NullImpl
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])
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println(fsa.textFiles)
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assertEquals(1,fsa.textFiles.size)
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assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.json"))
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}
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}
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