move to CoreDSL v2.0.3
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@ -66,10 +66,10 @@ class CoreDslJsonGenerator extends AbstractGenerator {
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def Iterable<Instruction> allInstr(CoreDef core) {
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val unique = newLinkedHashMap
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val instrList = if (core.contributingType.size == 0)
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val instrList = if (core.providedInstructionSets.size == 0)
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core.instructions
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else {
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val instrSets = core.contributingType?.map[InstructionSet i|i.allInstructionSets].flatten
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val instrSets = core.providedInstructionSets?.map[InstructionSet i|i.allInstructionSets].flatten
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val seen = newLinkedHashSet
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seen.addAll(instrSets)
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seen.map[InstructionSet i|i.instructions].flatten
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@ -97,11 +97,11 @@ class CoreDslJsonGenerator extends AbstractGenerator {
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def String getBitEncoding(Encoding encoding) '''«FOR field : encoding.fields»«field.regEx»«ENDFOR»'''
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def dispatch getRegEx(BitField i) '''«FOR idx : i.right.value.intValue .. i.left.value.intValue».«ENDFOR»'''
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def dispatch getRegEx(BitField i) '''«FOR idx : i.startIndex.value.intValue .. i.endIndex.value.intValue».«ENDFOR»'''
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def dispatch getRegEx(BitValue i) '''«i.value.toString(2)»'''
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def dispatch asString(BitField i) '''«i.name»[«i.left.value.intValue»:«i.right.value.intValue»]'''
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def dispatch asString(BitField i) '''«i.name»[«i.startIndex.value.intValue»:«i.endIndex.value.intValue»]'''
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def dispatch asString(BitValue i) {
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(i.value as BigIntegerWithRadix).toCString(2)
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