DBT-RISE/CoreDSL2JSON
8
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

cleanup warnings

Browse Source
This commit is contained in:
Eyck Jentzsch
2021-09-25 16:39:48 +02:00
parent 07831ef4fc
commit 450753930a
5 changed files with 1 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
com.minres.coredsl.json.tests/src/com/minres/coredsl/json/tests/CoreDslGenerationTest.xtend
View File

@@ -1,7 +1,6 @@
package com.minres.coredsl.json.tests
import com.google.inject.Inject
import com.minres.coredsl.coreDsl.CoreDef
import com.minres.coredsl.coreDsl.DescriptionContent
import org.eclipse.emf.ecore.util.EcoreUtil
import org.eclipse.xtext.generator.GeneratorContext
@@ -137,35 +136,4 @@ Core RV32I {
// '''.toString, fsa.textFiles.get(IFileSystemAccess::DEFAULT_OUTPUT+"Alice.java").toString
// )
}
@Test
def void expandCppFile() {
val content = parseHelper.parse(isa_rv32i)
assertNotNull(content)
val resource = content.eResource
EcoreUtil.resolveAll(resource);
assertEquals(0, resource.errors.size)
assertEquals(0, resource.warnings.size)
val CoreDef model = content.definitions.get(0) as CoreDef
assertNotNull(model)
val fsa = new InMemoryFileSystemAccess()
val quote1 = '<27><>'
val quote2 = '<27><>'
fsa.generateFile("vm_" + model.name.toLowerCase + ".in.cpp", "vm-out", '''
/* <20><>quote1<65><31>start generated code<64><65>quote2<65><32> */
InstructionDesriptor instr_descr[0] = {};
/* <20><>quote1<65><31>end generated code<64><65>quote2<65><32> */
''')
generator.doGenerate(model.eResource, fsa, new GeneratorContext => [
cancelIndicator = CancelIndicator.NullImpl
])
println(fsa.textFiles)
assertEquals(2,fsa.textFiles.size)
assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.txt"))
// assertEquals(
// '''
// public class Bob {
//
// }
// '''.toString, fsa.textFiles.get(IFileSystemAccess::DEFAULT_OUTPUT+"Bob.java").toString)
}
}

14
com.minres.coredsl.json.tests/src/com/minres/coredsl/json/tests/CoreDslGenerationUnitTest.xtend
View File

@@ -59,13 +59,6 @@ class CoreDslGenerationUnitTest{
}
'''.addInstructionContext.parse
validator.assertNoErrors(content)
val ref = '''
void CLI(){
{
if(rd == 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
}
}
'''
val fsa = new InMemoryFileSystemAccess()
generator.doGenerate(content.eResource, fsa, new GeneratorContext => [
cancelIndicator = CancelIndicator.NullImpl
@@ -93,13 +86,6 @@ class CoreDslGenerationUnitTest{
}
'''.addInstructionContext.parse
validator.assertNoErrors(content)
val ref = '''
void CLI(){
{
if(rd == 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
}
}
'''
val fsa = new InMemoryFileSystemAccess()
generator.doGenerate(content.eResource, fsa, new GeneratorContext => [
cancelIndicator = CancelIndicator.NullImpl