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update to latest CoreDSL 2.0.2

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This commit is contained in:
Eyck Jentzsch 2022-03-06 15:00:14 +01:00
parent 68373e580f
commit 369678b731
4 changed files with 28 additions and 61 deletions
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8
com.minres.coredsl.json.target/com.minres.coredsl.json.target.target
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@ -39,17 +39,13 @@
<unit id="org.codehaus.groovy25.feature.feature.group" version="0.0.0"/> <unit id="org.codehaus.groovy25.feature.feature.group" version="0.0.0"/>
<unit id="org.codehaus.groovy30.feature.feature.group" version="0.0.0"/> <unit id="org.codehaus.groovy30.feature.feature.group" version="0.0.0"/>
</location> </location>
<location includeAllPlatforms="false" includeConfigurePhase="false" includeMode="planner" includeSource="true" type="InstallableUnit">
<repository location="https://minres.com/download/repository/BundlePool"/>
<unit id="groovy-templates" version="3.0.7"/>
</location>
<location includeAllPlatforms="false" includeConfigurePhase="false" includeMode="planner" includeSource="true" type="InstallableUnit"> <location includeAllPlatforms="false" includeConfigurePhase="false" includeMode="planner" includeSource="true" type="InstallableUnit">
<repository location="https://download.eclipse.org/tools/orbit/downloads/drops/R20201130205003/repository"/> <repository location="https://download.eclipse.org/tools/orbit/downloads/drops/R20201130205003/repository"/>
<unit id="org.json" version="1.0.0.v201011060100"/> <unit id="org.json" version="1.0.0.v201011060100"/>
</location> </location>
<location includeAllPlatforms="false" includeConfigurePhase="false" includeMode="planner" includeSource="true" type="InstallableUnit"> <location includeAllPlatforms="false" includeConfigurePhase="false" includeMode="planner" includeSource="true" type="InstallableUnit">
<repository location="https://artifactory.minres.com/artifactory/eclipse/CoreDSL/2.0"/> <repository location="https://minres.github.io/CoreDSL/repository/2.0/2.0.2"/>
<unit id="com.minres.coredsl.feature.feature.group" version="2.0.1.202109261307"/> <unit id="com.minres.coredsl.feature.feature.group" version="2.0.2.202203061202"/>
</location> </location>
</locations> </locations>
</target> </target>

39
com.minres.coredsl.json.tests/src/com/minres/coredsl/json/tests/CoreDslGenerationTest.xtend
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@ -31,47 +31,44 @@ class CoreDslGenerationTest{
val isa_rv32i = ''' val isa_rv32i = '''
Core RV32I { Core RV32I {
constants { architectural_state {
unsigned int XLEN, FLEN; unsigned int XLEN, FLEN;
unsigned CSR_SIZE = 4096; unsigned CSR_SIZE = 4096;
unsigned REG_FILE_SIZE=32; unsigned REG_FILE_SIZE=32;
register unsigned<XLEN> PC [[is_pc]];
register unsigned<XLEN> X[REG_FILE_SIZE];
extern char MEM[1<<XLEN];
extern unsigned CSR[CSR_SIZE];
} }
registers { instructions [[hls]] {
[[is_pc]] int PC ;
int X[REG_FILE_SIZE];
}
address_spaces {
char MEM[1<<XLEN];
unsigned CSR[CSR_SIZE];
}
instructions {
ADDI { ADDI {
encoding: imm[11:0]s :: rs1[4:0] :: b000 :: rd[4:0] :: b0010011; encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
behavior: { behavior: {
X[rd] = X[rs1] + imm; X[rd] = X[rs1] + imm;
} }
} }
SLTI { SLTI {
encoding: imm[11:0]s :: rs1[4:0] :: b010 :: rd[4:0] :: b0010011; encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
behavior: { behavior: {
X[rd] = X[rs1] < imm? 1 : 0; X[rd] = X[rs1] < imm? 1 : 0;
} }
} }
SLTIU { SLTIU {
encoding: imm[11:0]s :: rs1[4:0] :: b011 :: rd[4:0] :: b0010011; encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
behavior: { behavior: {
X[rd] = X[rs1] < imm? 1 : 0; X[rd] = X[rs1] < imm? 1 : 0;
} }
} }
SW { SW {
encoding: imm[11:5]s :: rs2[4:0] :: rs1[4:0] :: b010 :: imm[4:0]s :: b0100011; encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
assembly:"{name(rs2)}, {imm}({name(rs1)})";
behavior: { behavior: {
int offset = X[rs1] + imm; int offset = X[rs1] + imm;
MEM[offset] = X[rs2]; MEM[offset] = X[rs2];
} }
} }
JAL[[no_cont]] { JAL[[no_cont]] {
encoding:imm[20:20]s :: imm[10:1]s :: imm[11:11]s :: imm[19:12]s :: rd[4:0] :: b1101111; encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
behavior: { behavior: {
if(rd!=0) X[rd] = (unsigned)PC; if(rd!=0) X[rd] = (unsigned)PC;
PC = PC+imm; PC = PC+imm;
@ -90,7 +87,7 @@ Core RV32I {
assertNotNull(result) assertNotNull(result)
assertEquals("RV32I", result.name) assertEquals("RV32I", result.name)
assertNull(result.superType) assertNull(result.superType)
assertEquals(4, result.declarations.size()) assertEquals(9, result.declarations.size())
assertNotNull(result.instructions) assertNotNull(result.instructions)
assertEquals(5, result.instructions.size) assertEquals(5, result.instructions.size)
@ -119,6 +116,7 @@ Core RV32I {
assertEquals(1, content.definitions.size) assertEquals(1, content.definitions.size)
val resource = content.eResource val resource = content.eResource
EcoreUtil.resolveAll(resource); EcoreUtil.resolveAll(resource);
validator.assertNoErrors(content)
assertEquals(0, resource.errors.size) assertEquals(0, resource.errors.size)
assertEquals(0, resource.warnings.size) assertEquals(0, resource.warnings.size)
val fsa = new InMemoryFileSystemAccess() val fsa = new InMemoryFileSystemAccess()
@ -127,13 +125,6 @@ Core RV32I {
]) ])
println(fsa.textFiles) println(fsa.textFiles)
assertEquals(1,fsa.textFiles.size) assertEquals(1,fsa.textFiles.size)
assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.txt")) assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.json"))
// assertEquals(
// '''
// public class Alice {
//
// }
// '''.toString, fsa.textFiles.get(IFileSystemAccess::DEFAULT_OUTPUT+"Alice.java").toString
// )
} }
} }

2
com.minres.coredsl.json/META-INF/MANIFEST.MF
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@ -5,7 +5,7 @@ Bundle-Vendor: MINRES Technologies GmbH
Bundle-Version: 2.0.0.qualifier Bundle-Version: 2.0.0.qualifier
Bundle-SymbolicName: com.minres.coredsl.json;singleton:=true Bundle-SymbolicName: com.minres.coredsl.json;singleton:=true
Bundle-ActivationPolicy: lazy Bundle-ActivationPolicy: lazy
Require-Bundle: com.minres.coredsl;bundle-version="1.0.0", Require-Bundle: com.minres.coredsl;bundle-version="2.0.0",
org.eclipse.equinox.common;bundle-version="3.5.0", org.eclipse.equinox.common;bundle-version="3.5.0",
org.eclipse.emf.ecore, org.eclipse.emf.ecore,
org.eclipse.emf.common, org.eclipse.emf.common,

34
com.minres.coredsl.json/src/com/minres/coredsl/json/CoreDslJsonGenerator.xtend
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@ -15,12 +15,12 @@ import com.minres.coredsl.coreDsl.Encoding
import com.minres.coredsl.coreDsl.BitField import com.minres.coredsl.coreDsl.BitField
import com.minres.coredsl.coreDsl.BitValue import com.minres.coredsl.coreDsl.BitValue
import java.util.List import java.util.List
import com.minres.coredsl.coreDsl.AttributeName
import com.minres.coredsl.coreDsl.ISA import com.minres.coredsl.coreDsl.ISA
import org.json.JSONObject import org.json.JSONObject
import org.json.JSONArray import org.json.JSONArray
import com.minres.coredsl.util.BigIntegerWithRadix import com.minres.coredsl.util.BigIntegerWithRadix
import com.minres.coredsl.coreDsl.Statement import com.minres.coredsl.coreDsl.Statement
import org.eclipse.xtext.resource.XtextResource
/** /**
* Generates code from your model files on save. * Generates code from your model files on save.
@ -35,14 +35,14 @@ class CoreDslJsonGenerator extends AbstractGenerator {
for (e : resource.allContents.toIterable.filter(CoreDef)) { for (e : resource.allContents.toIterable.filter(CoreDef)) {
val root = new JSONObject() val root = new JSONObject()
root.put('instructions', e.compile) root.put('instructions', e.compile)
fsa.generateFile(e.name + ".json", root.toString) fsa.generateFile(e.name + ".json", root.toString(2))
} }
} }
def Boolean isHls(Instruction inst){ def Boolean isHls(Instruction inst){
val instrSet = inst.eContainer as ISA; val instrSet = inst.eContainer as ISA;
!(inst.attributes.filter[it.type==AttributeName.HLS].isEmpty && !(inst.attributes.filter[it.type=='hls'].isEmpty &&
instrSet.attributes.filter[it.type==AttributeName.HLS].isEmpty) instrSet.commonInstructionAttributes.filter[it.type=='hls'].isEmpty)
} }
def JSONArray compile(CoreDef coreDef) { def JSONArray compile(CoreDef coreDef) {
val insts = coreDef.allInstr val insts = coreDef.allInstr
@ -53,35 +53,15 @@ class CoreDslJsonGenerator extends AbstractGenerator {
def JSONObject jsonDescr(Instruction inst){ def JSONObject jsonDescr(Instruction inst){
val ret = new JSONObject(); val ret = new JSONObject();
ret.put("decoding", inst.encoding.fields.map[it.asString].join(' ')) ret.put("decoding", inst.encoding.fields.map[it.asString].join('|'))
ret.put("name", inst.name); ret.put("name", inst.name);
ret.put('disassembly', inst.disass !== null? inst.name.toLowerCase + ' ' + inst.disass.toLowerCase : inst.name) ret.put('disassembly', inst.assembly !== null? inst.name.toLowerCase + ' ' + inst.assembly.toLowerCase : inst.name)
ret.put('execution', inst.behavior.source) ret.put('execution', inst.behavior.source)
ret.put('restrictions', '') ret.put('restrictions', '')
} }
def String getSource(Statement stmt){ def String getSource(Statement stmt){
// val c = CoreDslFactory.eINSTANCE.createDescriptionContent => [ (stmt.eResource as XtextResource).serializer.serialize(stmt)
// definitions += CoreDslFactory.eINSTANCE.createISA => [
// name = 'dummy'
// instructions += CoreDslFactory.eINSTANCE.createInstruction => [
// name = 'dummy'
// encoding = CoreDslFactory.eINSTANCE.createEncoding => [
// fields += CoreDslFactory.eINSTANCE.createBitField => [
// name = 'dummy'
// left = CoreDslFactory.eINSTANCE.createIntegerConstant => [ value= BigInteger.valueOf(32) ]
// right = CoreDslFactory.eINSTANCE.createIntegerConstant => [ value= BigInteger.ZERO ]
// ]
// ]
// behavior = stmt
// ]
// ]
// ]
// val rs = rsp.get
// val r = rs.createResource(URI.createURI("dummy.core_desc"))
// r.contents+=c
// c.serialize
stmt.toString
} }
def Iterable<Instruction> allInstr(CoreDef core) { def Iterable<Instruction> allInstr(CoreDef core) {