DBT-RISE/CoreDSL2JSON
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update to latest CoreDSL 2.0.2

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This commit is contained in:
Eyck Jentzsch
2022-03-06 15:00:14 +01:00
parent 68373e580f
commit 369678b731
4 changed files with 28 additions and 61 deletions
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41
com.minres.coredsl.json.tests/src/com/minres/coredsl/json/tests/CoreDslGenerationTest.xtend
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@@ -31,47 +31,44 @@ class CoreDslGenerationTest{
val isa_rv32i = '''
Core RV32I {
constants {
architectural_state {
unsigned int XLEN, FLEN;
unsigned CSR_SIZE = 4096;
unsigned REG_FILE_SIZE=32;
register unsigned<XLEN> PC [[is_pc]];
register unsigned<XLEN> X[REG_FILE_SIZE];
extern char MEM[1<<XLEN];
extern unsigned CSR[CSR_SIZE];
}
registers {
[[is_pc]] int PC ;
int X[REG_FILE_SIZE];
}
address_spaces {
char MEM[1<<XLEN];
unsigned CSR[CSR_SIZE];
}
instructions {
instructions [[hls]] {
ADDI {
encoding: imm[11:0]s :: rs1[4:0] :: b000 :: rd[4:0] :: b0010011;
encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] + imm;
}
}
SLTI {
encoding: imm[11:0]s :: rs1[4:0] :: b010 :: rd[4:0] :: b0010011;
encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] < imm? 1 : 0;
}
}
SLTIU {
encoding: imm[11:0]s :: rs1[4:0] :: b011 :: rd[4:0] :: b0010011;
encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] < imm? 1 : 0;
}
}
SW {
encoding: imm[11:5]s :: rs2[4:0] :: rs1[4:0] :: b010 :: imm[4:0]s :: b0100011;
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
assembly:"{name(rs2)}, {imm}({name(rs1)})";
behavior: {
int offset = X[rs1] + imm;
MEM[offset] = X[rs2];
}
}
JAL[[no_cont]] {
encoding:imm[20:20]s :: imm[10:1]s :: imm[11:11]s :: imm[19:12]s :: rd[4:0] :: b1101111;
encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
behavior: {
if(rd!=0) X[rd] = (unsigned)PC;
PC = PC+imm;
@@ -90,7 +87,7 @@ Core RV32I {
assertNotNull(result)
assertEquals("RV32I", result.name)
assertNull(result.superType)
assertEquals(4, result.declarations.size())
assertEquals(9, result.declarations.size())
assertNotNull(result.instructions)
assertEquals(5, result.instructions.size)
@@ -119,21 +116,15 @@ Core RV32I {
assertEquals(1, content.definitions.size)
val resource = content.eResource
EcoreUtil.resolveAll(resource);
validator.assertNoErrors(content)
assertEquals(0, resource.errors.size)
assertEquals(0, resource.warnings.size)
val fsa = new InMemoryFileSystemAccess()
generator.doGenerate(content.eResource, fsa, new GeneratorContext => [
cancelIndicator = CancelIndicator.NullImpl
])
println(fsa.textFiles)
println(fsa.textFiles)
assertEquals(1,fsa.textFiles.size)
assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.txt"))
// assertEquals(
// '''
// public class Alice {
//
// }
// '''.toString, fsa.textFiles.get(IFileSystemAccess::DEFAULT_OUTPUT+"Alice.java").toString
// )
assertTrue(fsa.textFiles.containsKey("DEFAULT_OUTPUTRV32I.json"))
}
}