forked from Firmware/Firmwares
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
// See LICENSE for license details.
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#ifndef _SIFIVE_PLATFORM_H
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#define _SIFIVE_PLATFORM_H
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// Some things missing from the official encoding.h
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x000003FFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x00000000000003FFUL
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#endif
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#define MTVEC_DIRECT 0X00
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#define MTVEC_VECTORED 0x01
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#define MTVEC_CLIC 0x02
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#define MTVEC_CLIC_VECT 0X03
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#include "sifive/const.h"
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#include "sifive/devices/gpio.h"
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#include "sifive/devices/clint.h"
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#include "sifive/devices/clic.h"
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#include "sifive/devices/pwm.h"
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#include "sifive/devices/spi.h"
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#include "sifive/devices/uart.h"
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// Memory map
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#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
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#define CLIC_HART0_ADDR _AC(0x02800000,UL)
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#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
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#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
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#define RAM_MEM_ADDR _AC(0x80000000,UL)
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#define RAM_MEM_SIZE _AC(0x10000,UL)
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#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
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#define SPI0_MEM_ADDR _AC(0x40000000,UL)
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#define SPI0_MEM_SIZE _AC(0x20000000,UL)
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#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
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#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
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//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
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#define UART0_CTRL_ADDR _AC(0x20000000,UL)
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// IOF masks
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// Interrupt numbers
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#define RESERVED_INT_BASE 0
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#define UART0_INT_BASE 1
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#define EXTERNAL_INT_BASE 2
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#define SPI0_INT_BASE 6
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#define GPIO_INT_BASE 7
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#define PWM0_INT_BASE 23
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// Helper functions
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#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
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#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
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#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
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#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
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#define CLIC0_REG8(offset) (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
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#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
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#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
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#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
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#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
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#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
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#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
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#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
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#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
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// Misc
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#define NUM_GPIO 16
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#define CLIC_NUM_INTERRUPTS 28 + 16
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#ifdef E20
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#define CLIC_CONFIG_BITS 2
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#else
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#define CLIC_CONFIG_BITS 4
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#endif
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#define HAS_BOARD_BUTTONS
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#include "coreplexip-arty.h"
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unsigned long get_cpu_freq(void);
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unsigned long get_timer_freq(void);
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uint64_t get_timer_value(void);
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#endif /* _SIFIVE_PLATFORM_H */
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