forked from Firmware/Firmwares
116 lines
3.3 KiB
C++
116 lines
3.3 KiB
C++
#include "hello_raven.h"
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#include "delay.h"
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#include "bsp.h"
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#include "plic/plic_driver.h"
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#include <cstdio>
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#include <cstdint>
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#include <array>
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#define IOF_ENABLE_TERMINAL (0x30000)
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typedef void (*function_ptr_t) (void);
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//! Instance data for the PLIC.
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plic_instance_t g_plic;
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std::array<function_ptr_t,PLIC_NUM_INTERRUPTS> g_ext_interrupt_handlers;
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char * end = (char *)0x80001000; // TODO: end supposed to be a RAM section according to the linker file falsh.lds, but for some reason it's not initialized
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/*! \brief external interrupt handler
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*
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* routes the peripheral interrupts to the the respective handler
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*
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*/
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extern "C" void handle_m_ext_interrupt() {
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plic_source int_num = PLIC_claim_interrupt(&g_plic);
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if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS))
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g_ext_interrupt_handlers[int_num]();
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else
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exit(1 + (uintptr_t) int_num);
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PLIC_complete_interrupt(&g_plic, int_num);
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}
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/*! \brief dummy interrupt handler
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*
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*/
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void no_interrupt_handler (void) {};
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/*! \brief configure the per-interrupt handler
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*
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*/
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void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) {
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g_ext_interrupt_handlers[irq_num] = handler;
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// Priority must be set > 0 to trigger the interrupt.
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PLIC_set_priority(&g_plic, irq_num, prio);
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// Have to enable the interrupt both at the GPIO level, and at the PLIC level.
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PLIC_enable_interrupt(&g_plic, irq_num);
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}
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static void msi_interrupt_handler(){
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int * local_mem_base = (int *) end;
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int hartid = read_csr(mhartid);
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int val_a = *local_mem_base;
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int val_b = *(local_mem_base+1);
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int sum = val_a + val_b;
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*(local_mem_base+100) = sum;
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if (sum == 0xF)
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printf("HW thread ID %d: sum of A+B=0x%x\n", hartid, sum);
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else {
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printf("HW thread ID %d: sum of A+B is not 0x%x. Test FAILED!!!\n", hartid, sum);
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}
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}
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/*!\brief initializes platform
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*
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*/
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void platform_init(){
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// UART init section TODO: clarify how to get the functions from init.c?
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GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
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UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
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F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ);
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printf("core freq at %d Hz\n", F_CPU);
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// initialie interupt & trap handling
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write_csr(mtvec, &trap_entry);
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PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0);
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// Disable the machine & timer interrupts until setup is done.
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler;
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configure_irq(1, msi_interrupt_handler);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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// Enable the Machine-External bit in MIE
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set_csr(mie, MIP_MEIP);
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}
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/*! \brief main function
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*
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*/
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int main() {
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volatile int * target_mem_base = (int *)(end + 0x10000000);
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int * local_mem_base = (int *) end;
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int * plic_b_pending = (int *)(0xC0000000+PLIC_PENDING_OFFSET);
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int hartid = read_csr(mhartid);
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platform_init();
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if (hartid == 0) {
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int val_a = 5;
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int val_b = 0xA;
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*target_mem_base = val_a;
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*(target_mem_base+1) = val_b;
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*(plic_b_pending) = 2;
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printf("HW thread ID %d: write value A=0x%x and value B=0x%x to thread 1\n", hartid, val_a, val_b);
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}
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delayUS(100);
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printf("End of execution");
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return 0;
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}
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