forked from Firmware/Firmwares
126 lines
4.4 KiB
C++
126 lines
4.4 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Thu Oct 01 15:45:55 CEST 2020
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// * spn_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#pragma once
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#include <util/bit_field.h>
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#include <cstdint>
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#define SPN_CNTL_REG_START_RESULT_CHECK 0x00
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#define SPN_CNTL_REG_OFFSET 0x10
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#define SPN_CNTL_REG_LENGTH 0x20
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#define SPN_CNTL_REG_OUTPUT_ADDR 0x30
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#define SPN_CNTL_REG_INPUT_ADDR 0x40
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#define SPN_CNTL_REG_NUM_INPUT_SAMPLES 0x50
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#define SPN_CNTL_REG_START_DATA_TRANS 0x60
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#define SPN_CNTL_REG_OUTPUT_ADDR2 0x70
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#define SPN_CNTL_REG_XSPN_COUNT 0x80
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#define SPN_CNTL_REG_BATCH_SIZE 0x90
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#define SPN_CNTL_REG_NUM_ITERATIONS 0xA0
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template<uint32_t BASE_ADDR>
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class spn_checker_regs {
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public:
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// storage declarations
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// BEGIN_BF_DECL(start_t, uint32_t);
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// BF_FIELD(start, 0, 1);
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// END_BF_DECL() r_start;
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uint32_t r_start_result_check;
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uint32_t r_offset;
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uint32_t r_length;
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uint32_t r_output_addr;
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uint32_t r_output_addr2;
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uint32_t r_input_addr;
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uint32_t r_num_input_samples;
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uint32_t r_start_data_trans;
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uint32_t r_xspn_count;
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uint32_t r_batch_size;
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uint32_t r_num_iterations;
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static inline uint32_t& start_result_check_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_RESULT_CHECK);
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}
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static inline uint32_t & offset_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OFFSET);
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}
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static inline uint32_t & length_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_LENGTH);
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}
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static inline uint32_t & output_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR);
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}
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static inline uint32_t & output_addr2_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR2);
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}
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static inline uint32_t & input_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_INPUT_ADDR);
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}
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static inline uint32_t & num_input_samples_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_INPUT_SAMPLES);
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}
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static inline uint32_t& start_data_trans_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_DATA_TRANS);
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}
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static inline uint32_t& xspn_count_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_XSPN_COUNT);
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}
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static inline uint32_t& batch_size_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_BATCH_SIZE);
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}
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static inline uint32_t& num_iterations_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_ITERATIONS);
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}
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};
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