forked from Firmware/Firmwares
253 lines
6.8 KiB
C
253 lines
6.8 KiB
C
// See LICENSE file for license details
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#include "platform.h"
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#ifdef PRCI_BASE_ADDR
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#include "fe300prci/fe300prci_driver.h"
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#include <unistd.h>
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#define rdmcycle(x) { \
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uint32_t lo, hi, hi2; \
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__asm__ __volatile__ ("1:\n\t" \
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"csrr %0, mcycleh\n\t" \
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"csrr %1, mcycle\n\t" \
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"csrr %2, mcycleh\n\t" \
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"bne %0, %2, 1b\n\t" \
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: "=r" (hi), "=r" (lo), "=r" (hi2)) ; \
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*(x) = lo | ((uint64_t) hi << 32); \
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}
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uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
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{
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uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
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uint32_t end_mtime = start_mtime + mtime_ticks + 1;
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// Make sure we won't get rollover.
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while (end_mtime < start_mtime){
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start_mtime = CLINT_REG(CLINT_MTIME);
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end_mtime = start_mtime + mtime_ticks + 1;
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}
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// Don't start measuring until mtime edge.
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uint32_t tmp = start_mtime;
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do {
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start_mtime = CLINT_REG(CLINT_MTIME);
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} while (start_mtime == tmp);
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uint64_t start_mcycle;
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rdmcycle(&start_mcycle);
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while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
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uint64_t end_mcycle;
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rdmcycle(&end_mcycle);
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uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
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uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
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return (uint32_t) freq & 0xFFFFFFFF;
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}
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void PRCI_use_hfrosc(int div, int trim)
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{
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// Make sure the HFROSC is running at its default setting
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// It is OK to change this even if we are running off of it.
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PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
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while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
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}
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void PRCI_use_pll(int refsel, int bypass,
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int r, int f, int q, int finaldiv,
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int hfroscdiv, int hfrosctrim)
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{
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// Ensure that we aren't running off the PLL before we mess with it.
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if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
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// Make sure the HFROSC is running at its default setting
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PRCI_use_hfrosc(4, 16);
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}
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// Set PLL Source to be HFXOSC if desired.
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uint32_t config_value = 0;
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config_value |= PLL_REFSEL(refsel);
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if (bypass) {
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// Bypass
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config_value |= PLL_BYPASS(1);
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// If we don't have an HFXTAL, this doesn't really matter.
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// Set our Final output divide to divide-by-1:
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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} else {
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// To overclock, use the hfrosc
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if (hfrosctrim >= 0 && hfroscdiv >= 0) {
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PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
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}
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// Set DIV Settings for PLL
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// (Legal values of f_REF are 6-48MHz)
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// Set DIVR to divide-by-2 to get 8MHz frequency
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// (legal values of f_R are 6-12 MHz)
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config_value |= PLL_BYPASS(1);
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config_value |= PLL_R(r);
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// Set DIVF to get 512Mhz frequncy
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// There is an implied multiply-by-2, 16Mhz.
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// So need to write 32-1
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// (legal values of f_F are 384-768 MHz)
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config_value |= PLL_F(f);
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// Set DIVQ to divide-by-2 to get 256 MHz frequency
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// (legal values of f_Q are 50-400Mhz)
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config_value |= PLL_Q(q);
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// Set our Final output divide to divide-by-1:
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if (finaldiv == 1){
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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} else {
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
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}
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// Un-Bypass the PLL.
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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// Wait for PLL Lock
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// Note that the Lock signal can be glitchy.
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// Need to wait 100 us
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// RTC is running at 32kHz.
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// So wait 4 ticks of RTC.
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uint32_t now = CLINT_REG(CLINT_MTIME);
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while (CLINT_REG(CLINT_MTIME) - now < 4) ;
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// Now it is safe to check for PLL Lock
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while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
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}
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// Switch over to PLL Clock source
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PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
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// If we're running off HFXOSC, turn off the HFROSC to
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// save power.
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if (refsel) {
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PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
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}
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}
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void PRCI_use_default_clocks()
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{
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// Turn off the LFROSC
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AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
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// Use HFROSC
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PRCI_use_hfrosc(4, 16);
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}
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void PRCI_use_hfxosc(uint32_t finaldiv)
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{
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PRCI_use_pll(1, // Use HFXTAL
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1, // Bypass = 1
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0, // PLL settings don't matter
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0, // PLL settings don't matter
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0, // PLL settings don't matter
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finaldiv,
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-1,
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-1);
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}
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// This is a generic function, which
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// doesn't span the entire range of HFROSC settings.
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// It only adjusts the trim, which can span a hundred MHz or so.
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// This function does not check the legality of the PLL settings
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// at all, and it is quite possible to configure invalid PLL settings
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// this way.
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// It returns the actual measured CPU frequency.
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uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
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{
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uint32_t hfrosctrim = 0;
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uint32_t hfroscdiv = 4;
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uint32_t prev_trim = 0;
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// In this function we use PLL settings which
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// will give us a 32x multiplier from the output
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// of the HFROSC source to the output of the
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// PLL. We first measure our HFROSC to get the
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// right trim, then finally use it as the PLL source.
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// We should really check here that the f_cpu
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// requested is something in the limit of the PLL. For
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// now that is up to the user.
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// This will undershoot for frequencies not divisible by 16.
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uint32_t desired_hfrosc_freq = (f_cpu/ 16);
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PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
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// Ignore the first run (for icache reasons)
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uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
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cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
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uint32_t prev_freq = cpu_freq;
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while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
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prev_trim = hfrosctrim;
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prev_freq = cpu_freq;
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hfrosctrim ++;
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PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
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cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
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}
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// We couldn't go low enough
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if (prev_freq > desired_hfrosc_freq){
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
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cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
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return cpu_freq;
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}
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// We couldn't go high enough
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if (cpu_freq < desired_hfrosc_freq){
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
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cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
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return cpu_freq;
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}
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// Check for over/undershoot
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switch(target) {
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case(PRCI_FREQ_CLOSEST):
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if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
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} else {
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
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}
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break;
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case(PRCI_FREQ_UNDERSHOOT):
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
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break;
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default:
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PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
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}
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cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
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return cpu_freq;
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}
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#endif
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