forked from Firmware/Firmwares
fixes TGC5L settings
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3217871752
commit
ca1adccb2b
@ -9,10 +9,10 @@ add_custom_target(fw-hello-world ALL
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USES_TERMINAL
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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add_custom_target(fw-dhrystone ALL
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/dhrystone BOARD=${TARGET} ISA=${ISA}
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/dhrystone BOARD=${BOARD} ISA=${ISA}
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USES_TERMINAL
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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add_custom_target(fw-coremark ALL
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark/cm PORT_DIR=../tgc BOARD=${TARGET} ISA=${ISA}
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark/cm PORT_DIR=../tgc BOARD=${BOARD} ISA=${ISA}
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USES_TERMINAL
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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4
bare-metal-bsp/env/TGC5L/link.lds
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4
bare-metal-bsp/env/TGC5L/link.lds
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@ -4,8 +4,8 @@ ENTRY( _start )
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MEMORY
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{
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flash (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64k
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ram (wxa!ri) : ORIGIN = 0x80010000, LENGTH = 64k
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flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 256M
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ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 1M
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}
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PHDRS
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8
bare-metal-bsp/env/start.S
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8
bare-metal-bsp/env/start.S
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@ -5,6 +5,8 @@
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.type _start,@function
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_start:
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la gp, trap_entry
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csrw mtvec, gp
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.option push
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.option norelax
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la gp, __global_pointer$
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@ -18,8 +20,8 @@ _start:
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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sw t0, (a1)
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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@ -35,11 +37,11 @@ _start:
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2:
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/* Call global constructors */
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#ifdef HAVE_INIT_FINI
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//#ifdef HAVE_INIT_FINI
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la a0, __libc_fini_array
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call atexit
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call __libc_init_array
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#endif
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//#endif
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#ifndef __riscv_float_abi_soft
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/* Enable FPU */
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li t0, MSTATUS_FS
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