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First configuration of the XSPNController

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This commit is contained in:
Stanislaw Kaushanski 2020-11-04 17:41:56 +01:00
parent 4720c923cd
commit 8249a0417e
4 changed files with 37 additions and 27 deletions
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2
raven_spn/bsp/env/freedom-e300-hifive1/flash.lds vendored
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@ -5,7 +5,7 @@ ENTRY( _start )
MEMORY MEMORY
{ {
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K
} }
PHDRS PHDRS

BIN
raven_spn/raven_spn
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34
raven_spn/src/raven_spn.cpp
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@ -49,17 +49,7 @@ void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1)
static void msi_interrupt_handler(){ static void msi_interrupt_handler(){
int * local_mem_base = (int *) 0x80000100; int * local_mem_base = (int *) 0x80000100;
int hartid = read_csr(mhartid); printf("INterrupt handler call\n");
int val_a = *local_mem_base;
int val_b = *(local_mem_base+1);
int sum = val_a + val_b;
*(local_mem_base+100) = sum;
if (sum == 0xF)
printf("HW thread ID %d: sum of A+B=0x%x\n", hartid, sum);
else {
printf("HW thread ID %d: sum of A+B is not 0x%x. Test FAILED!!!\n", hartid, sum);
}
} }
/*!\brief initializes platform /*!\brief initializes platform
@ -94,16 +84,22 @@ void platform_init(){
int main() { int main() {
platform_init(); platform_init();
printf("Configure SPN HW accelerator\n"); spn::mode_reg() = 1;
spn::mode_reg() = 0; spn::start_reg() = 1;
spn::input_length_reg() = 1; printf("READOUT reuslt:0x%x\n", spn::readout_reg());
spn::input_addr_reg() = 0x80000000; spn::interrupt_reg() = 1;
spn::output_addr_reg() = 0x80001000;
spn::num_of_in_beats_reg() = 1;
spn::num_of_out_beats_reg() = 1;
spn::input_length_reg() = 5;
spn::input_addr_reg() = 0x80000000;
spn::output_addr_reg() = 0x80100000;
spn::num_of_in_beats_reg() = 5;
spn::num_of_out_beats_reg() = 1;
spn::mode_reg() = 0;
uint32_t result_addr = spn::output_addr_reg();
spn::start_reg() = 1;
printf("Start SPN HW accelerator\n"); printf("Start SPN HW accelerator\n");
spn::start_reg()=1;
delayUS(100); delayUS(100);

28
raven_spn/src/spn_regs.h
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@ -40,23 +40,25 @@
#include <cstdint> #include <cstdint>
#define SPN_REG_START 0x00 #define SPN_REG_START 0x00
#define SPN_REG_RET_VAL 0x10 #define SPN_REG_READOUT 0x10
#define SPN_REG_MODE 0x20 #define SPN_REG_MODE 0x20
#define SPN_REG_INPUT_LENGTH 0x30 #define SPN_REG_INPUT_LENGTH 0x30
#define SPN_REG_INPUT_ADDR 0x40 #define SPN_REG_INPUT_ADDR 0x40
#define SPN_REG_OUTPUT_ADDR 0x50 #define SPN_REG_OUTPUT_ADDR 0x50
#define SPN_REG_NUM_OF_INPUT_BEATS 0x60 #define SPN_REG_NUM_OF_INPUT_BEATS 0x60
#define SPN_REG_NUM_OF_OUTPUT_BEATS 0x70 #define SPN_REG_NUM_OF_OUTPUT_BEATS 0x70
#define SPN_REG_INTERRUPT 0x0C
template<uint32_t BASE_ADDR> template<uint32_t BASE_ADDR>
class spn_regs { class spn_regs {
public: public:
// storage declarations // storage declarations
BEGIN_BF_DECL(start_t, uint32_t); // BEGIN_BF_DECL(start_t, uint32_t);
BF_FIELD(start, 0, 1); // BF_FIELD(start, 0, 1);
END_BF_DECL() r_start; // END_BF_DECL() r_start;
uint32_t r_start;
uint32_t r_ret_val; uint32_t r_readout;
uint32_t r_mode; uint32_t r_mode;
@ -70,8 +72,15 @@ public:
uint32_t r_num_of_output_beats; uint32_t r_num_of_output_beats;
static inline start_t& start_reg(){ // static inline start_t& start_reg(){
return *reinterpret_cast<start_t*>(BASE_ADDR+SPN_REG_START); // return *reinterpret_cast<start_t*>(BASE_ADDR+SPN_REG_START);
// }
static inline uint32_t& start_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_START);
}
static inline uint32_t & readout_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_READOUT);
} }
static inline uint32_t & mode_reg(){ static inline uint32_t & mode_reg(){
@ -97,6 +106,11 @@ public:
static inline uint32_t & num_of_out_beats_reg(){ static inline uint32_t & num_of_out_beats_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_OUTPUT_BEATS); return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_OUTPUT_BEATS);
} }
static inline uint32_t & interrupt_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INTERRUPT);
}
}; };
#endif // _SPN_REGS_H_ #endif // _SPN_REGS_H_