stas/Firmwares
1
0
Fork 0
forked from Firmware/Firmwares
Code Issues Pull Requests Projects Releases Wiki Activity

adds some consistency fixes for variable ISA settings

Browse Source
This commit is contained in:
Eyck Jentzsch
2023-12-02 17:41:14 +01:00
parent 8c1c2766e8
commit 6ff0161882
7 changed files with 16 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
bare-metal-bsp/env/common-gcc.mk vendored
View File

@@ -24,7 +24,7 @@ INCLUDES += -I$(PLATFORM_DIR)
TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin/
LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
LDFLAGS += -T $(LINKER_SCRIPT) -Wl,-Map=$(TARGET).map -nostartfiles
LDFLAGS += -T $(LINKER_SCRIPT) -Wl,--no-warn-rwx-segments -Wl,-Map=$(TARGET).map -nostartfiles
LDFLAGS += -L$(ENV_DIR)
# --specs=nano.specs

2
bare-metal-bsp/env/iss/link.lds vendored
View File

@@ -4,7 +4,7 @@ ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x00000020, LENGTH = 1M
flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M
ram (wxa!ri) : ORIGIN = 0x10000000, LENGTH = 16K
}

1
bare-metal-bsp/env/rtl/link.lds vendored
View File

@@ -169,7 +169,6 @@ SECTIONS
PROVIDE( _sp = . );
} >ram AT>ram :ram
#PROVIDE( tohost = 0x00018000 );
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

10
benchmarks/coremark/tgc/core_portme.mak
View File

@@ -18,19 +18,19 @@
ISA?=imc
RISCV_ARCH:=rv32$(ISA)
RISCV_ABI:=ilp32
TRIPLET?=riscv64-unknown-elf
# Flag : OUTFLAG
# Use this flag to define how to to get an executable (e.g -o)
OUTFLAG= -o
# Flag : CC
# Use this flag to define compiler to use
CC = riscv32-unknown-elf-gcc
CC = $(TRIPLET)-gcc
# Flag : LD
# Use this flag to define compiler to use
LD = riscv32-unknown-elf-gcc
LD = $(TRIPLET)-gcc
# Flag : AS
# Use this flag to define compiler to use
AS = riscv32-unknown-elf-as
AS = $(TRIPLET)-as
# Flag : CFLAGS
# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
PORT_CFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs \
@@ -44,7 +44,7 @@ SEPARATE_COMPILE=1
# Flag : SEPARATE_COMPILE
# You must also define below how to create an object file, and how to link.
OBJOUT = -o
LFLAGS =
LFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
#--specs=nano.specs -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
ASFLAGS =
OFLAG = -o

1
benchmarks/dhrystone/Makefile
View File

@@ -20,6 +20,5 @@ LDFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medlow -Wl,--wrap
TOOL_DIR=$(dir $(compiler))
TRIPLET=riscv32-unknown-elf
BSP_BASE = ../../bare-metal-bsp
include $(BSP_BASE)/env/common-gcc.mk

2
benchmarks/dhrystone/dhry_stubs.c
View File

@@ -16,7 +16,7 @@ void __wrap_scanf(const char* fmt, int* n)
extern volatile uint32_t tohost;
void __wrap_exit(int n){
void exit(int n){
tohost = 0x1;
for (;;);
}

8
hello-world/Makefile
View File

@@ -1,5 +1,7 @@
TARGET = hello
ISA?=imc
C_SRCS = $(wildcard *.c)
HEADERS = $(wildcard *.h)
OPT ?= -O2
@@ -7,8 +9,12 @@ CFLAGS += $(OPT) -g
BOARD=iss
LINK_TARGET=link
RISCV_ARCH:=rv32e
RISCV_ARCH:=rv32$(ISA)
ifeq ($(ISA),e)
RISCV_ABI:=ilp32e
else
RISCV_ABI:=ilp32
endif
LDFLAGS += -g -Wl,--wrap=printf
compiler := $(shell which riscv64-unknown-elf-gcc)