forked from Firmware/Firmwares
149 lines
4.5 KiB
C++
149 lines
4.5 KiB
C++
|
#include "hello_raven.h"
|
||
|
#include "delay.h"
|
||
|
#include "bsp.h"
|
||
|
#include "plic/plic_driver.h"
|
||
|
|
||
|
#include <cstdio>
|
||
|
#include <cstdint>
|
||
|
|
||
|
#include "hifive1_io.h"
|
||
|
|
||
|
|
||
|
|
||
|
#define IOF_ENABLE_TERMINAL (0x30000)
|
||
|
|
||
|
|
||
|
typedef void (*function_ptr_t) (void);
|
||
|
//! Instance data for the PLIC.
|
||
|
plic_instance_t g_plic;
|
||
|
std::array<function_ptr_t,PLIC_NUM_INTERRUPTS> g_ext_interrupt_handlers;
|
||
|
|
||
|
|
||
|
char * end = (char *)0x80001000; // TODO: end supposed to be a RAM section according to the linker file falsh.lds, but for some reason it's not initialized
|
||
|
|
||
|
/*! \brief external interrupt handler
|
||
|
*
|
||
|
* routes the peripheral interrupts to the the respective handler
|
||
|
*
|
||
|
*/
|
||
|
extern "C" void handle_m_ext_interrupt() {
|
||
|
plic_source int_num = PLIC_claim_interrupt(&g_plic);
|
||
|
if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS))
|
||
|
g_ext_interrupt_handlers[int_num]();
|
||
|
else
|
||
|
exit(1 + (uintptr_t) int_num);
|
||
|
PLIC_complete_interrupt(&g_plic, int_num);
|
||
|
}
|
||
|
/*! \brief mtime interval interrupt
|
||
|
*
|
||
|
*/
|
||
|
extern "C" void handle_m_time_interrupt(){
|
||
|
clear_csr(mie, MIP_MTIP);
|
||
|
// Reset the timer for 3s in the future.
|
||
|
// This also clears the existing timer interrupt.
|
||
|
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
|
||
|
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
|
||
|
uint64_t now = *mtime;
|
||
|
uint64_t then = now + RTC_FREQ;
|
||
|
*mtimecmp = then;
|
||
|
// Re-enable the timer interrupt.
|
||
|
set_csr(mie, MIP_MTIP);
|
||
|
}
|
||
|
/*! \brief dummy interrupt handler
|
||
|
*
|
||
|
*/
|
||
|
void no_interrupt_handler (void) {};
|
||
|
/*! \brief configure the per-interrupt handler
|
||
|
*
|
||
|
*/
|
||
|
void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) {
|
||
|
g_ext_interrupt_handlers[irq_num] = handler;
|
||
|
// Priority must be set > 0 to trigger the interrupt.
|
||
|
PLIC_set_priority(&g_plic, irq_num, prio);
|
||
|
// Have to enable the interrupt both at the GPIO level, and at the PLIC level.
|
||
|
PLIC_enable_interrupt(&g_plic, irq_num);
|
||
|
}
|
||
|
|
||
|
static void msi_interrupt_handler(){
|
||
|
int * local_mem_base = (int *) end;
|
||
|
int hartid = read_csr(mhartid);
|
||
|
|
||
|
int val_a = *local_mem_base;
|
||
|
int val_b = *(local_mem_base+1);
|
||
|
int sum = val_a + val_b;
|
||
|
*(local_mem_base+100) = sum;
|
||
|
if (sum == 0xF)
|
||
|
printf("HW thread ID %d: sum of A+B=0x%x\n", hartid, sum);
|
||
|
else {
|
||
|
printf("HW thread ID %d: sum of A+B is not 0x%x. Test FAILED!!!\n", hartid, sum);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/*!\brief initializes platform
|
||
|
*
|
||
|
*/
|
||
|
void platform_init(){
|
||
|
// configure clocks
|
||
|
PRCI_use_hfxosc(1); // is equivalent to
|
||
|
qspi1::sckdiv_reg() = 8;
|
||
|
|
||
|
F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ);
|
||
|
printf("core freq at %d Hz\n", F_CPU);
|
||
|
// initialie interupt & trap handling
|
||
|
write_csr(mtvec, &trap_entry);
|
||
|
|
||
|
PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0);
|
||
|
// Disable the machine & timer interrupts until setup is done.
|
||
|
clear_csr(mie, MIP_MEIP);
|
||
|
clear_csr(mie, MIP_MTIP);
|
||
|
for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler;
|
||
|
configure_irq(1, msi_interrupt_handler);
|
||
|
// Set the machine timer to go off in 1 second.
|
||
|
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
|
||
|
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
|
||
|
uint64_t now = *mtime;
|
||
|
uint64_t then = now + RTC_FREQ;
|
||
|
*mtimecmp = then;
|
||
|
// Enable the Machine-External bit in MIE
|
||
|
set_csr(mie, MIP_MEIP);
|
||
|
// Enable the Machine-Timer bit in MIE
|
||
|
set_csr(mie, MIP_MTIP);
|
||
|
// Enable interrupts in general.
|
||
|
set_csr(mstatus, MSTATUS_MIE);
|
||
|
}
|
||
|
|
||
|
/*! \brief main function
|
||
|
*
|
||
|
*/
|
||
|
int main() {
|
||
|
volatile int * target_mem_base = (int *)(end + 0x10000000);
|
||
|
int * local_mem_base = (int *) end;
|
||
|
int * plic_b_pending = (int *)(0xA0000000+PLIC_PENDING_OFFSET);
|
||
|
|
||
|
int * local_sync_bit = (int *)(local_mem_base + 10);
|
||
|
int * target_sync_bit = (int *)(target_mem_base + 10);
|
||
|
|
||
|
int hartid = read_csr(mhartid);
|
||
|
|
||
|
*local_sync_bit = 0;
|
||
|
GPIO_REG(GPIO_IOF_EN) |= IOF_ENABLE_TERMINAL; // enable GPIO connection to the terminal
|
||
|
platform_init();
|
||
|
// Enable the Machine-External bit in MIE
|
||
|
set_csr(mie, MIP_MEIP);
|
||
|
|
||
|
if (hartid == 0) {
|
||
|
int val_a = 5;
|
||
|
int val_b = 0xA;
|
||
|
*target_mem_base = val_a;
|
||
|
*(target_mem_base+1) = val_b;
|
||
|
*(plic_b_pending) = 2;
|
||
|
printf("HW thread ID %d: write value A=0x%x and value B=0x%x to thread 1\n", hartid, val_a, val_b);
|
||
|
}
|
||
|
|
||
|
*local_sync_bit++;
|
||
|
while (*target_sync_bit < *local_sync_bit);
|
||
|
|
||
|
printf("End of execution");
|
||
|
return 0;
|
||
|
}
|