78 lines
2.5 KiB
C++
78 lines
2.5 KiB
C++
/*
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* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _PLATFORM_H_
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#define _PLATFORM_H_
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#include "minres/irq.h"
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#include "minres/timer.h"
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#include <array>
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#include <cci_configuration>
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#include <memory>
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#include <minres/aclint.h>
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#include <minres/gpio.h>
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#include <minres/qspi.h>
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#include <minres/uart.h>
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#include <scc/memory.h>
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#include <scc/router.h>
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#include <scc/utilities.h>
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#include <sysc/communication/sc_clock.h>
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#include <sysc/communication/sc_signal_ports.h>
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#include <sysc/core_complex.h>
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#include <sysc/kernel/sc_module.h>
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#include <sysc/kernel/sc_time.h>
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#include <sysc/utils/sc_vector.h>
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#include <tlm/scc/tlm_signal_sockets.h>
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namespace tgc_vp {
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class system : public sc_core::sc_module {
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public:
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SC_HAS_PROCESS(system); // NOLINT
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o", 32};
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
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sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
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sc_core::sc_out<bool> uart0_tx_o{"uart0_tx_o"};
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sc_core::sc_in<bool> uart0_rx_i{"uart0_rx_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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spi::spi_pkt_initiator_socket<> mspi0{"mspi0"};
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_in<bool> erst_n{"erst_n"};
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system(sc_core::sc_module_name nm);
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private:
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sysc::tgfs::core_complex<> core_complex{"core_complex"};
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scc::router<> ahb_router, apbBridge;
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vpvper::minres::gpio_tl gpio0{"gpio0"};
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vpvper::minres::uart_tl uart0{"uart0"};
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vpvper::minres::timer_tl timer0{"timer0"};
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vpvper::minres::aclint_tl aclint{"aclint"};
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vpvper::minres::irq_tl irq_ctrl{"irq_ctrl"};
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vpvper::minres::qspi_tl qspi{"qspi"};
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scc::memory_tl<1_kB, scc::LT> boot_rom{"boot_rom"};
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scc::memory_tl<32_kB, scc::LT> main_ram{"main_ram"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"},
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msip_int_s{"msip_int_s"};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32},
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local_int_s{"local_int_s", 16};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
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void gen_reset();
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#include "tgc_vp/gen/PipelinedMemoryBusToApbBridge.h"
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};
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} // namespace tgc_vp
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#endif /* _PLATFORM_H_ */
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