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This commit is contained in:
Eyck Jentzsch
2022-04-11 09:22:28 +02:00
commit cc687eaf4b
103 changed files with 7211 additions and 0 deletions
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26
src/tgc_vp/gen/platform_mmap.h Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _PLATFORM_MMAP_H_
#define _PLATFORM_MMAP_H_
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<32>, 13> platfrom_mmap = {{
{clint.socket, 0x2000000, 0xc000},
{plic.socket, 0xc000000, 0x200008},
{aon.socket, 0x10000000, 0x150},
{prci.socket, 0x10008000, 0x14},
{gpio0.socket, 0x10012000, 0x44},
{uart0.socket, 0x10013000, 0x1c},
{qspi0.socket, 0x10014000, 0x78},
{pwm0.socket, 0x10015000, 0x30},
{uart1.socket, 0x10023000, 0x1c},
{qspi1.socket, 0x10024000, 0x78},
{pwm1.socket, 0x10025000, 0x30},
{qspi2.socket, 0x10034000, 0x78},
{pwm2.socket, 0x10035000, 0x30},
}};
#endif /* _PLATFORM_MMAP_H_ */

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src/tgc_vp/platform.rdl Normal file
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`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "pwm.rdl"
`include "plic.rdl"
`include "aon.rdl"
`include "prci.rdl"
`include "clint.rdl"
addrmap e300_plat_t {
lsb0;
clint_regs clint @0x02000000;
plic_regs plic @0x0C000000;
aon_regs aon @0x10000000;
prci_regs prci @0x10008000;
gpio_regs gpio0 @0x10012000;
uart_regs uart0 @0x10013000;
spi_regs qspi0 @0x10014000;
pwm_regs pwm0 @0x10015000;
uart_regs uart1 @0x10023000;
spi_regs qspi1 @0x10024000;
pwm_regs pwm1 @0x10025000;
spi_regs qspi2 @0x10034000;
pwm_regs pwm2 @0x10035000;
} e300_plat;

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src/tgc_vp/rst_gen.h Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <systemc>
namespace tgc_vp {
class rst_gen : public sc_core::sc_module {
SC_HAS_PROCESS(rst_gen);
public:
rst_gen(sc_core::sc_module_name const& nm) {
SC_THREAD(run);
}
sc_core::sc_out<bool> rst_n{"rst_n"};
private:
void run(){
rst_n.write(false);
wait(100_ns);
rst_n.write(true);
}
};
} /* namespace tgc_vp */

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src/tgc_vp/system.cpp Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "tgc_vp/system.h"
namespace tgc_vp {
using namespace sc_core;
using namespace vpvper::sifive;
using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(router, platfrom_mmap.size() + 2, 1)
, NAMEDC(qspi0_ptr, spi, spi_impl::beh)
, NAMEDC(qspi1_ptr, spi, spi_impl::beh)
, NAMEDC(qspi2_ptr, spi, spi_impl::beh)
, qspi0(*qspi0_ptr)
, qspi1(*qspi1_ptr)
, qspi2(*qspi2_ptr)
{
auto& qspi0 = *qspi0_ptr;
auto& qspi1 = *qspi1_ptr;
auto& qspi2 = *qspi2_ptr;
core_complex.initiator(router.target[0]);
size_t i = 0;
for (const auto &e : platfrom_mmap) {
router.initiator.at(i)(e.target);
router.set_target_range(i, e.start, e.size);
i++;
}
router.initiator.at(i)(mem_qspi.target);
router.set_target_range(i, 0x20000000, 512_MB);
router.initiator.at(++i)(mem_ram.target);
router.set_target_range(i, 0x80000000, 128_kB);
uart1.clk_i(tlclk_s);
qspi0.clk_i(tlclk_s);
qspi1.clk_i(tlclk_s);
qspi2.clk_i(tlclk_s);
pwm0.clk_i(tlclk_s);
pwm1.clk_i(tlclk_s);
pwm2.clk_i(tlclk_s);
gpio0.clk_i(tlclk_s);
plic.clk_i(tlclk_s);
aon.clk_i(tlclk_s);
aon.lfclkc_o(lfclk_s);
prci.hfclk_o(tlclk_s); // clock driver
clint.tlclk_i(tlclk_s);
clint.lfclk_i(lfclk_s);
core_complex.clk_i(tlclk_s);
uart0.rst_i(rst_s);
uart1.rst_i(rst_s);
qspi0.rst_i(rst_s);
qspi1.rst_i(rst_s);
qspi2.rst_i(rst_s);
pwm0.rst_i(rst_s);
pwm1.rst_i(rst_s);
pwm2.rst_i(rst_s);
gpio0.rst_i(rst_s);
plic.rst_i(rst_s);
aon.rst_o(rst_s);
prci.rst_i(rst_s);
clint.rst_i(rst_s);
core_complex.rst_i(rst_s);
aon.erst_n_i(erst_n);
clint.mtime_int_o(mtime_int_s);
clint.msip_int_o(msie_int_s);
plic.global_interrupts_i(global_int_s);
plic.core_interrupt_o(core_int_s);
core_complex.sw_irq_i(msie_int_s);
core_complex.timer_irq_i(mtime_int_s);
core_complex.global_irq_i(core_int_s);
core_complex.local_irq_i(local_int_s);
pins_i(gpio0.pins_i);
gpio0.pins_o(pins_o);
uart0.irq_o(global_int_s[3]);
gpio0.iof0_i[5](qspi1.sck_o);
gpio0.iof0_i[3](qspi1.mosi_o);
qspi1.miso_i(gpio0.iof0_o[4]);
gpio0.iof0_i[2](qspi1.scs_o[0]);
gpio0.iof0_i[9](qspi1.scs_o[2]);
gpio0.iof0_i[10](qspi1.scs_o[3]);
qspi0.irq_o(global_int_s[5]);
qspi1.irq_o(global_int_s[6]);
qspi2.irq_o(global_int_s[7]);
s_dummy_sck_i[0](uart1.tx_o);
uart1.rx_i(s_dummy_sck_o[0]);
uart1.irq_o(global_int_s[4]);
gpio0.iof1_i[0](pwm0.cmpgpio_o[0]);
gpio0.iof1_i[1](pwm0.cmpgpio_o[1]);
gpio0.iof1_i[2](pwm0.cmpgpio_o[2]);
gpio0.iof1_i[3](pwm0.cmpgpio_o[3]);
gpio0.iof1_i[10](pwm2.cmpgpio_o[0]);
gpio0.iof1_i[11](pwm2.cmpgpio_o[1]);
gpio0.iof1_i[12](pwm2.cmpgpio_o[2]);
gpio0.iof1_i[13](pwm2.cmpgpio_o[3]);
gpio0.iof1_i[19](pwm1.cmpgpio_o[0]);
gpio0.iof1_i[20](pwm1.cmpgpio_o[1]);
gpio0.iof1_i[21](pwm1.cmpgpio_o[2]);
gpio0.iof1_i[22](pwm1.cmpgpio_o[3]);
pwm0.cmpip_o[0](global_int_s[40]);
pwm0.cmpip_o[1](global_int_s[41]);
pwm0.cmpip_o[2](global_int_s[42]);
pwm0.cmpip_o[3](global_int_s[43]);
pwm1.cmpip_o[0](global_int_s[44]);
pwm1.cmpip_o[1](global_int_s[45]);
pwm1.cmpip_o[2](global_int_s[46]);
pwm1.cmpip_o[3](global_int_s[47]);
pwm2.cmpip_o[0](global_int_s[48]);
pwm2.cmpip_o[1](global_int_s[49]);
pwm2.cmpip_o[2](global_int_s[50]);
pwm2.cmpip_o[3](global_int_s[51]);
for (auto &sock : s_dummy_sck_i) sock.error_if_no_callback = false;
}
} /* namespace sysc */

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src/tgc_vp/system.h Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _PLATFORM_H_
#define _PLATFORM_H_
#include <sifive/aon.h>
#include <sifive/clint.h>
#include <sifive/gpio.h>
#include <sifive/plic.h>
#include <sifive/prci.h>
#include <sifive/pwm.h>
#include <sifive/spi.h>
#include <sysc/core_complex.h>
#include <sifive/uart.h>
#include <sifive/uart_terminal.h>
#include <cci_configuration>
#include <scc/memory.h>
#include <scc/router.h>
#include <scc/utilities.h>
#include <tlm/scc/tlm_signal_sockets.h>
#include <array>
#include <memory>
#include <sysc/kernel/sc_module.h>
namespace tgc_vp {
class system : public sc_core::sc_module {
public:
SC_HAS_PROCESS(system);// NOLINT
sc_core::sc_vector<tlm::scc::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o{"pins_o", 32};
sc_core::sc_vector<tlm::scc::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i{"pins_i", 32};
sc_core::sc_in<bool> erst_n{"erst_n"};
system(sc_core::sc_module_name nm);
private:
sysc::tgfs::core_complex core_complex{"core_complex"};
scc::router<> router;
vpvper::sifive::uart_terminal uart0{"uart0"};
vpvper::sifive::uart uart1{"uart1"};
std::unique_ptr<vpvper::sifive::spi> qspi0_ptr, qspi1_ptr, qspi2_ptr;
vpvper::sifive::pwm pwm0{"pwm0"}, pwm1{"pwm1"}, pwm2{"pwm2"};
vpvper::sifive::gpio gpio0{"gpio0"};
vpvper::sifive::plic plic{"plic"};
vpvper::sifive::aon aon{"aon"};
vpvper::sifive::prci prci{"prci"};
vpvper::sifive::clint clint{"clint"};
using mem_qspi_t = scc::memory<512_MB, 32>;
mem_qspi_t mem_qspi{"mem_qspi"};
using mem_ram_t = scc::memory<128_kB, 32>;
mem_ram_t mem_ram{"mem_ram"};
sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> tlclk_s{"tlclk_s"};
sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> lfclk_s{"lfclk_s"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msie_int_s{"msie_int_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> global_int_s{"global_int_s", 256}, local_int_s{"local_int_s", 16};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> s_dummy_sck_i{"s_dummy_sck_i", 16};
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> s_dummy_sck_o{"s_dummy_sck_o", 16};
protected:
void gen_reset();
vpvper::sifive::spi& qspi0;
vpvper::sifive::spi& qspi1;
vpvper::sifive::spi& qspi2;
#include "tgc_vp/gen/platform_mmap.h"
};
} /* namespace sysc */
#endif /* _PLATFORM_H_ */

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src/tgc_vp/tb.cpp Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "tgc_vp/tb.h"
namespace tgc_vp {
SC_HAS_PROCESS(tb);
tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
top.erst_n(rst_n);
rst_gen.rst_n(rst_n);
for (auto i = 0U; i < gpio_s.size(); ++i) {
gpio_s[i].in(top.pins_o[i]);
top.pins_i[i](gpio_s[i].out);
}
// terminal
terminal.tx_o(gpio_s[16].in);
gpio_s[17].out(terminal.rx_i);
}
}

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src/tgc_vp/tb.h Normal file
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/*
* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef SRC_TGC_VP_TB_H_
#define SRC_TGC_VP_TB_H_
#include <generic/terminal.h>
#include <systemc>
#include "tgc_vp/rst_gen.h"
#include "tgc_vp/system.h"
namespace tgc_vp {
class tb : public sc_core::sc_module {
public:
tb(sc_core::sc_module_name const& nm);
tgc_vp::system top{"top"};
tgc_vp::rst_gen rst_gen{"rst_gen"};
sc_core::sc_vector<tlm::scc::tlm_signal<sc_dt::sc_logic>> gpio_s{"gpio_s", 32};
sc_core::sc_signal<bool> rst_n{"rst_n"};
vpvper::generic::terminal terminal{"terminal"};
};
} /* namespace tgc_vp */
#endif /* SRC_TGC_VP_TB_H_ */