adds Flash model

This commit is contained in:
Eyck-Alexander Jentzsch 2025-03-28 23:20:10 +01:00
parent 715b8349d6
commit c7df003b02
4 changed files with 73 additions and 1 deletions

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@ -18,6 +18,7 @@ add_executable(${PROJECT_NAME}
CLIParser.cpp
tgc_vp/tb.cpp
tgc_vp/system.cpp
tgc_vp/Flash.cpp
)
target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR})
target_force_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc_sc)

66
src/tgc_vp/Flash.cpp Normal file
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@ -0,0 +1,66 @@
#include <algorithm>
#include <cstddef>
#include <iterator>
#include <limits>
#include <scc/memory.h>
#include <vector>
template <unsigned long long SIZE, unsigned BUSWIDTH> class flash : public scc::memory<SIZE, scc::LT> {
public:
flash(const sc_core::sc_module_name& nm);
cci::cci_param<unsigned> FB_BUFFER_COUNT{"FB_BUFFER_COUNT", 2, "number of flash buffers"};
cci::cci_param<unsigned> FB_SIZE{"FB_SIZE", 2, "represents the flash line size normalized to the bus data width"};
cci::cci_param<unsigned> FR_DELAY{
"FR_DELAY", 0,
"When a read is requested to the flash, it takes FR_DELAY cycles longer to respond in case of a buffer miss"};
cci::cci_param<sc_core::sc_time> FR_DELAY_TIME{"FR_DELAY_TIME", sc_core::SC_ZERO_TIME,
"When a read is requested to the flash, it takes FR_DELAY_TIME "
"duration longer to respond in case of a buffer miss"};
private:
std::vector<unsigned> buffers;
std::vector<unsigned> timestamps;
unsigned counter{0};
int handle_operation(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
bool buffer_hit(uint64_t addr);
};
template <unsigned long long SIZE, unsigned BUSWIDTH>
flash<SIZE, BUSWIDTH>::flash(const sc_core::sc_module_name& nm)
: scc::memory<SIZE, scc::LT>(nm)
, buffers(FB_BUFFER_COUNT, std::numeric_limits<unsigned>::max())
, timestamps(FB_BUFFER_COUNT, 0) {
this->set_operation_callback(
[this](scc::memory<SIZE, scc::LT>& mem, tlm::tlm_generic_payload& gp, sc_core::sc_time& delay) -> int {
tlm::tlm_command cmd = gp.get_command();
auto res = 0;
if(cmd == tlm::TLM_READ_COMMAND) {
::sc_dt::uint64 adr = gp.get_address();
unsigned len = gp.get_data_length();
delay += buffer_hit(adr) ? sc_core::SC_ZERO_TIME
: this->clk_i.get_interface() ? this->clk_i->read() * FR_DELAY
: FR_DELAY_TIME;
res = mem.handle_operation(gp, delay);
} else if(!sc_core::sc_time_stamp().value()) {
res = mem.handle_operation(gp, delay);
}
gp.set_dmi_allowed(false);
return res;
});
}
template <unsigned long long SIZE, unsigned BUSWIDTH> bool flash<SIZE, BUSWIDTH>::buffer_hit(uint64_t addr) {
auto current_cache_start = addr - addr % (BUSWIDTH / 8 * FB_SIZE);
auto it = std::find(buffers.begin(), buffers.end(), current_cache_start);
if(it != buffers.end()) {
size_t index = std::distance(buffers.begin(), it);
timestamps[index] = ++counter;
return true;
} else {
auto it = std::min_element(timestamps.begin(), timestamps.end());
size_t lru_index = std::distance(timestamps.begin(), it);
buffers[lru_index] = current_cache_start;
timestamps[lru_index] = ++counter;
return false;
}
}

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@ -16,7 +16,7 @@ using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(ahb_router, 3, 2)
, NAMED(ahb_router, 4, 2)
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
core_complex.ibus(ahb_router.target[0]);
core_complex.dbus(ahb_router.target[1]);
@ -27,6 +27,8 @@ system::system(sc_core::sc_module_name nm)
ahb_router.set_target_range(1, 0x80000000, 32_kB);
ahb_router.initiator.at(2)(apbBridge.target[0]);
ahb_router.set_target_range(2, 0xF0000000, 256_MB);
ahb_router.initiator.at(3)(flash_mem.target);
ahb_router.set_target_range(3, 0xD0000000, 8_kB);
size_t i = 0;
for(const auto& e : PipelinedMemoryBusToApbBridge_map) {
@ -44,6 +46,7 @@ system::system(sc_core::sc_module_name nm)
boot_rom.clk_i(clk_i);
core_complex.clk_i(clk_i);
main_ram.clk_i(clk_i);
flash_mem.clk_i(clk_i);
gpio0.rst_i(rst_s);
uart0.rst_i(rst_s);

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@ -27,6 +27,7 @@
#include <sysc/utils/sc_vector.h>
#include <tlm/scc/tlm_signal_sockets.h>
#include "Flash.cpp"
namespace tgc_vp {
class system : public sc_core::sc_module {
@ -63,6 +64,7 @@ private:
scc::memory<1_kB, scc::LT> boot_rom{"boot_rom"};
scc::memory<32_kB, scc::LT> main_ram{"main_ram"};
flash<8_kB, 32> flash_mem{"flash_mem"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"},
msip_int_s{"msip_int_s"};