adds Flash model
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715b8349d6
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c7df003b02
@ -18,6 +18,7 @@ add_executable(${PROJECT_NAME}
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CLIParser.cpp
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tgc_vp/tb.cpp
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tgc_vp/system.cpp
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tgc_vp/Flash.cpp
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)
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target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR})
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target_force_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc_sc)
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66
src/tgc_vp/Flash.cpp
Normal file
66
src/tgc_vp/Flash.cpp
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@ -0,0 +1,66 @@
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#include <algorithm>
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#include <cstddef>
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#include <iterator>
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#include <limits>
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#include <scc/memory.h>
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#include <vector>
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template <unsigned long long SIZE, unsigned BUSWIDTH> class flash : public scc::memory<SIZE, scc::LT> {
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public:
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flash(const sc_core::sc_module_name& nm);
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cci::cci_param<unsigned> FB_BUFFER_COUNT{"FB_BUFFER_COUNT", 2, "number of flash buffers"};
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cci::cci_param<unsigned> FB_SIZE{"FB_SIZE", 2, "represents the flash line size normalized to the bus data width"};
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cci::cci_param<unsigned> FR_DELAY{
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"FR_DELAY", 0,
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"When a read is requested to the flash, it takes FR_DELAY cycles longer to respond in case of a buffer miss"};
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cci::cci_param<sc_core::sc_time> FR_DELAY_TIME{"FR_DELAY_TIME", sc_core::SC_ZERO_TIME,
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"When a read is requested to the flash, it takes FR_DELAY_TIME "
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"duration longer to respond in case of a buffer miss"};
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private:
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std::vector<unsigned> buffers;
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std::vector<unsigned> timestamps;
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unsigned counter{0};
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int handle_operation(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
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bool buffer_hit(uint64_t addr);
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};
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template <unsigned long long SIZE, unsigned BUSWIDTH>
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flash<SIZE, BUSWIDTH>::flash(const sc_core::sc_module_name& nm)
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: scc::memory<SIZE, scc::LT>(nm)
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, buffers(FB_BUFFER_COUNT, std::numeric_limits<unsigned>::max())
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, timestamps(FB_BUFFER_COUNT, 0) {
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this->set_operation_callback(
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[this](scc::memory<SIZE, scc::LT>& mem, tlm::tlm_generic_payload& gp, sc_core::sc_time& delay) -> int {
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tlm::tlm_command cmd = gp.get_command();
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auto res = 0;
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if(cmd == tlm::TLM_READ_COMMAND) {
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::sc_dt::uint64 adr = gp.get_address();
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unsigned len = gp.get_data_length();
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delay += buffer_hit(adr) ? sc_core::SC_ZERO_TIME
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: this->clk_i.get_interface() ? this->clk_i->read() * FR_DELAY
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: FR_DELAY_TIME;
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res = mem.handle_operation(gp, delay);
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} else if(!sc_core::sc_time_stamp().value()) {
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res = mem.handle_operation(gp, delay);
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}
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gp.set_dmi_allowed(false);
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return res;
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});
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}
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template <unsigned long long SIZE, unsigned BUSWIDTH> bool flash<SIZE, BUSWIDTH>::buffer_hit(uint64_t addr) {
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auto current_cache_start = addr - addr % (BUSWIDTH / 8 * FB_SIZE);
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auto it = std::find(buffers.begin(), buffers.end(), current_cache_start);
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if(it != buffers.end()) {
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size_t index = std::distance(buffers.begin(), it);
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timestamps[index] = ++counter;
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return true;
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} else {
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auto it = std::min_element(timestamps.begin(), timestamps.end());
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size_t lru_index = std::distance(timestamps.begin(), it);
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buffers[lru_index] = current_cache_start;
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timestamps[lru_index] = ++counter;
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return false;
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}
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}
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@ -16,7 +16,7 @@ using namespace sysc::tgfs;
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system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(ahb_router, 3, 2)
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, NAMED(ahb_router, 4, 2)
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, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
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core_complex.ibus(ahb_router.target[0]);
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core_complex.dbus(ahb_router.target[1]);
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@ -27,6 +27,8 @@ system::system(sc_core::sc_module_name nm)
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ahb_router.set_target_range(1, 0x80000000, 32_kB);
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ahb_router.initiator.at(2)(apbBridge.target[0]);
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ahb_router.set_target_range(2, 0xF0000000, 256_MB);
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ahb_router.initiator.at(3)(flash_mem.target);
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ahb_router.set_target_range(3, 0xD0000000, 8_kB);
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size_t i = 0;
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for(const auto& e : PipelinedMemoryBusToApbBridge_map) {
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@ -44,6 +46,7 @@ system::system(sc_core::sc_module_name nm)
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boot_rom.clk_i(clk_i);
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core_complex.clk_i(clk_i);
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main_ram.clk_i(clk_i);
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flash_mem.clk_i(clk_i);
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gpio0.rst_i(rst_s);
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uart0.rst_i(rst_s);
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@ -27,6 +27,7 @@
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#include <sysc/utils/sc_vector.h>
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#include <tlm/scc/tlm_signal_sockets.h>
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#include "Flash.cpp"
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namespace tgc_vp {
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class system : public sc_core::sc_module {
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@ -63,6 +64,7 @@ private:
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scc::memory<1_kB, scc::LT> boot_rom{"boot_rom"};
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scc::memory<32_kB, scc::LT> main_ram{"main_ram"};
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flash<8_kB, 32> flash_mem{"flash_mem"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"},
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msip_int_s{"msip_int_s"};
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