adds new mnrs vp modeled after ehrenberg
This commit is contained in:
parent
1c50084d9a
commit
c12b00e52e
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@ -21,7 +21,7 @@ add_executable(${PROJECT_NAME}
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)
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target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR})
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target_force_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc_sc)
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target_link_libraries(${PROJECT_NAME} PUBLIC vpvper_generic vpvper_sifive ${BOOST_program_options_LIBRARY})
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target_link_libraries(${PROJECT_NAME} PUBLIC vpvper_generic vpvper_minres ${BOOST_program_options_LIBRARY})
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if(TARGET Boost::program_options)
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target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
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else()
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@ -1,22 +1,21 @@
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/*
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* Copyright (c) 2023 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Created on: «new Date»
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* * «componentDefinition.effectiveName».h Author: <RDL Generator>
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*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-08 14:41:56 UTC
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* by peakrdl_mnrs version 1.2.2
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*/
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#pragma once
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// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
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const std::array<scc::target_memory_map_entry<32>, 7> PipelinedMemoryBusToApbBridge_map = {{
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const std::array<scc::target_memory_map_entry<scc::LT>, 6> PipelinedMemoryBusToApbBridge_map = {{
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{ gpio0.socket, 0x0, 0xc },
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{ uart0.socket, 0x1000, 0x14 },
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{ timer0.socket, 0x20000, 0x1c },
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{ aclint.socket, 0x30000, 0xc000 },
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{ irq_ctrl.socket, 0x40000, 0x8 },
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{ qspi.socket, 0x50000, 0x5c },
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{ bootloader.socket, 0x80000, 0x400 },
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//{ bootloader.socket, 0x80000, 0x400 },
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}} ;
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@ -5,124 +5,91 @@
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*/
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#include "tgc_vp/system.h"
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#include "minres/timer.h"
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#include "minres/uart.h"
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#include "scc/utilities.h"
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namespace tgc_vp {
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using namespace sc_core;
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using namespace vpvper::sifive;
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using namespace vpvper::minres;
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using namespace sysc::tgfs;
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system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(router, platfrom_mmap.size() + 2, 2)
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{
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core_complex.ibus(router.target[0]);
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core_complex.dbus(router.target[1]);
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, NAMED(ahb_router, 3, 2)
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, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1){
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core_complex.ibus(ahb_router.target[0]);
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core_complex.dbus(ahb_router.target[1]);
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ahb_router.initiator.at(0)(qspi.xip_sck);
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ahb_router.set_target_range(0, 0xE0000000, 16_MB);
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ahb_router.initiator.at(1)(mem_ram.target);
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ahb_router.set_target_range(1, 0x80000000, 32_kB);
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ahb_router.initiator.at(2)(apbBridge.target[0]);
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ahb_router.set_target_range(2, 0xF0000000, 256_MB);
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size_t i = 0;
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for (const auto &e : platfrom_mmap) {
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router.initiator.at(i)(e.target);
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router.set_target_range(i, e.start, e.size);
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for (const auto &e : PipelinedMemoryBusToApbBridge_map) {
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apbBridge.initiator.at(i)(e.target);
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apbBridge.set_target_range(i, e.start, e.size);
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i++;
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}
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router.initiator.at(i)(mem_qspi.target);
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router.set_target_range(i, 0x20000000, 512_MB);
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router.initiator.at(++i)(mem_ram.target);
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router.set_target_range(i, 0x80000000, 128_kB);
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uart1.clk_i(tlclk_s);
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qspi0.clk_i(tlclk_s);
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qspi1.clk_i(tlclk_s);
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qspi2.clk_i(tlclk_s);
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pwm0.clk_i(tlclk_s);
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pwm1.clk_i(tlclk_s);
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pwm2.clk_i(tlclk_s);
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gpio0.clk_i(tlclk_s);
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plic.clk_i(tlclk_s);
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aon.clk_i(tlclk_s);
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aon.lfclkc_o(lfclk_s);
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prci.hfclk_o(tlclk_s); // clock driver
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clint.tlclk_i(tlclk_s);
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clint.lfclk_i(lfclk_s);
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core_complex.clk_i(tlclk_s);
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mem_qspi.clk_i(tlclk_s);
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mem_ram.clk_i(tlclk_s);
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gpio0.clk_i(clk_i);
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uart0.clk_i(clk_i);
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timer0.clk_i(clk_i);
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aclint.clk_i(clk_i);
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irq_ctrl.clk_i(clk_i);
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qspi.clk_i(clk_i);
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core_complex.clk_i(clk_i);
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//mem_ram.clk_i(clk_i);
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uart0.rst_i(rst_s);
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uart1.rst_i(rst_s);
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qspi0.rst_i(rst_s);
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qspi1.rst_i(rst_s);
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qspi2.rst_i(rst_s);
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pwm0.rst_i(rst_s);
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pwm1.rst_i(rst_s);
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pwm2.rst_i(rst_s);
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gpio0.rst_i(rst_s);
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plic.rst_i(rst_s);
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aon.rst_o(rst_s);
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prci.rst_i(rst_s);
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clint.rst_i(rst_s);
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uart0.rst_i(rst_s);
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timer0.rst_i(rst_s);
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aclint.rst_i(rst_s);
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irq_ctrl.rst_i(rst_s);
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qspi.rst_i(rst_s);
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core_complex.rst_i(rst_s);
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aon.erst_n_i(erst_n);
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aclint.mtime_int_o(mtime_int_s);
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aclint.msip_int_o(msip_int_s);
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irq_ctrl.irq_o(core_int_s);
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irq_ctrl.pending_irq_i(irq_int_s);
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clint.mtime_int_o(mtime_int_s);
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clint.msip_int_o(msie_int_s);
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uart0.irq_o(irq_int_s[0]);
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timer0.interrupt_o[0](irq_int_s[1]);
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timer0.interrupt_o[1](irq_int_s[2]);
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qspi.irq_o(irq_int_s[3]);
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plic.global_interrupts_i(global_int_s);
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plic.core_interrupt_o(core_int_s);
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core_complex.sw_irq_i(msie_int_s);
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core_complex.timer_irq_i(mtime_int_s);
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core_complex.ext_irq_i(core_int_s);
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core_complex.local_irq_i(local_int_s);
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core_complex.sw_irq_i(msip_int_s);
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pins_i(gpio0.pins_i);
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gpio0.pins_i(pins_i);
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gpio0.pins_o(pins_o);
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gpio0.oe_o(pins_oe_o);
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uart0.irq_o(global_int_s[3]);
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uart0.tx_o(uart0_tx_o);
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uart0.rx_i(uart0_rx_i);
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gpio0.iof0_i[5](qspi1.sck_o);
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gpio0.iof0_i[3](qspi1.mosi_o);
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qspi1.miso_i(gpio0.iof0_o[4]);
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gpio0.iof0_i[2](qspi1.scs_o[0]);
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gpio0.iof0_i[9](qspi1.scs_o[2]);
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gpio0.iof0_i[10](qspi1.scs_o[3]);
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timer0.clear_i(t0_clear_i);
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timer0.tick_i(t0_tick_i);
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qspi0.irq_o(global_int_s[5]);
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qspi1.irq_o(global_int_s[6]);
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qspi2.irq_o(global_int_s[7]);
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qspi.ssclk_o(ssclk_o);
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qspi.dq_o(dq_o);
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qspi.dq_i(dq_i);
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qspi.oe_o(dq_oe_o);
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gpio0.iof0_i[16](uart1.tx_o);
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uart1.rx_i(gpio0.iof0_o[17]);
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uart1.irq_o(global_int_s[4]);
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gpio0.iof1_i[0](pwm0.cmpgpio_o[0]);
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gpio0.iof1_i[1](pwm0.cmpgpio_o[1]);
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gpio0.iof1_i[2](pwm0.cmpgpio_o[2]);
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gpio0.iof1_i[3](pwm0.cmpgpio_o[3]);
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gpio0.iof1_i[10](pwm2.cmpgpio_o[0]);
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gpio0.iof1_i[11](pwm2.cmpgpio_o[1]);
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gpio0.iof1_i[12](pwm2.cmpgpio_o[2]);
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gpio0.iof1_i[13](pwm2.cmpgpio_o[3]);
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gpio0.iof1_i[19](pwm1.cmpgpio_o[0]);
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gpio0.iof1_i[20](pwm1.cmpgpio_o[1]);
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gpio0.iof1_i[21](pwm1.cmpgpio_o[2]);
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gpio0.iof1_i[22](pwm1.cmpgpio_o[3]);
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pwm0.cmpip_o[0](global_int_s[40]);
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pwm0.cmpip_o[1](global_int_s[41]);
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pwm0.cmpip_o[2](global_int_s[42]);
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pwm0.cmpip_o[3](global_int_s[43]);
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pwm1.cmpip_o[0](global_int_s[44]);
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pwm1.cmpip_o[1](global_int_s[45]);
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pwm1.cmpip_o[2](global_int_s[46]);
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pwm1.cmpip_o[3](global_int_s[47]);
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pwm2.cmpip_o[0](global_int_s[48]);
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pwm2.cmpip_o[1](global_int_s[49]);
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pwm2.cmpip_o[2](global_int_s[50]);
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pwm2.cmpip_o[3](global_int_s[51]);
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SC_METHOD(gen_reset);
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sensitive << erst_n;
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}
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void system::gen_reset(){
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if(erst_n.read())
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rst_s = 0;
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else rst_s = 1;
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}
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} /* namespace sysc */
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@ -7,20 +7,21 @@
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#ifndef _PLATFORM_H_
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#define _PLATFORM_H_
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#include <sifive/aon.h>
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#include <sifive/clint.h>
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#include <sifive/gpio.h>
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#include <sifive/plic.h>
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#include <sifive/prci.h>
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#include <sifive/pwm.h>
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#include <sifive/spi.h>
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#include "minres/irq.h"
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#include "minres/timer.h"
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#include <minres/aclint.h>
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#include <minres/gpio.h>
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#include <minres/qspi.h>
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#include <sysc/communication/sc_clock.h>
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#include <sysc/communication/sc_signal_ports.h>
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#include <sysc/core_complex.h>
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#include <sifive/uart.h>
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#include <sifive/uart_terminal.h>
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#include <minres/uart.h>
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#include <cci_configuration>
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#include <scc/memory.h>
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#include <scc/router.h>
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#include <scc/utilities.h>
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#include <sysc/kernel/sc_time.h>
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#include <sysc/utils/sc_vector.h>
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#include <tlm/scc/tlm_signal_sockets.h>
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#include <array>
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#include <memory>
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@ -32,8 +33,19 @@ class system : public sc_core::sc_module {
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public:
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SC_HAS_PROCESS(system);// NOLINT
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sc_core::sc_vector<tlm::scc::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o{"pins_o", 32};
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sc_core::sc_vector<tlm::scc::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i{"pins_i", 32};
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o",32};
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
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sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
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sc_core::sc_out<bool> uart0_tx_o {"uart0_tx_o"};
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sc_core::sc_in<bool> uart0_rx_i {"uart0_rx_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
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sc_core::sc_out<bool> ssclk_o{"ssclk_o"};
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sc_core::sc_vector<sc_core::sc_out<bool>> dq_o{"dq_o", 4};
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sc_core::sc_vector<sc_core::sc_out<bool>> dq_oe_o{"dq_oe_o", 4};
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sc_core::sc_vector<sc_core::sc_in<bool>> dq_i{"dq_i", 4};
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_in<bool> erst_n{"erst_n"};
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@ -41,32 +53,24 @@ public:
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private:
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sysc::tgfs::core_complex core_complex{"core_complex"};
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scc::router<> router;
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vpvper::sifive::uart_terminal uart0{"uart0"};
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vpvper::sifive::uart uart1{"uart1"};
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vpvper::sifive::spi qspi0{"qspi0"}, qspi1{"qspi1"}, qspi2{"qspi2"};
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vpvper::sifive::pwm pwm0{"pwm0"}, pwm1{"pwm1"}, pwm2{"pwm2"};
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vpvper::sifive::gpio gpio0{"gpio0"};
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vpvper::sifive::plic plic{"plic"};
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vpvper::sifive::aon aon{"aon"};
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vpvper::sifive::prci prci{"prci"};
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vpvper::sifive::clint clint{"clint"};
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scc::router<> ahb_router, apbBridge;
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vpvper::minres::gpio_tl gpio0{"gpio0"};
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vpvper::minres::uart_tl uart0{"uart0"};
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vpvper::minres::timer_tl timer0{"timer0"};
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vpvper::minres::aclint_tl aclint{"aclint"};
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vpvper::minres::irq_tl irq_ctrl{"irq_ctrl"};
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vpvper::minres::qspi_tl qspi{"qspi"};
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using mem_qspi_t = scc::memory<512_MB, scc::LT>;
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mem_qspi_t mem_qspi{"mem_qspi"};
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using mem_ram_t = scc::memory<128_kB, scc::LT>;
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mem_ram_t mem_ram{"mem_ram"};
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//scc::memory<1_kB, scc::LT> bootloader{"bootloader"};
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scc::memory<32_kB, scc::LT> mem_ram {"mem_ram"};
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sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> tlclk_s{"tlclk_s"};
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sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> lfclk_s{"lfclk_s"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msie_int_s{"msie_int_s"};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> global_int_s{"global_int_s", 256}, local_int_s{"local_int_s", 16};
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sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16};
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sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
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void gen_reset();
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#include "tgc_vp/gen/platform_mmap.h"
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#include "tgc_vp/gen/PipelinedMemoryBusToApbBridge.h"
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};
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} /* namespace sysc */
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@ -5,20 +5,25 @@
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*/
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#include "tgc_vp/tb.h"
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#include <sysc/kernel/sc_time.h>
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namespace tgc_vp {
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SC_HAS_PROCESS(tb);
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tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
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top.erst_n(rst_n);
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rst_gen.rst_n(rst_n);
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for (auto i = 0U; i < gpio_s.size(); ++i) {
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gpio_s[i].in(top.pins_o[i]);
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top.pins_i[i](gpio_s[i].out);
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}
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#ifndef WIN32
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// terminal
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terminal.tx_o(gpio_s[16].in);
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gpio_s[17].out(terminal.rx_i);
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#endif
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top.pins_o(pins_o);
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top.pins_i(pins_i);
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top.pins_oe_o(pins_oe_o);
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top.uart0_rx_i(uart0_rx_i);
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top.uart0_tx_o(uart0_tx_o);
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top.t0_clear_i(t0_clear_i);
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top.t0_tick_i(t0_tick_i);
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top.ssclk_o(ssclk_o);
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top.dq_o(dq_o);
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top.dq_i(dq_i);
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top.dq_oe_o(dq_oe_o);
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top.clk_i(clk_i);
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clk_i = 10_ns;
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}
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}
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@ -19,11 +19,19 @@ public:
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tb(sc_core::sc_module_name const& nm);
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tgc_vp::system top{"top"};
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tgc_vp::rst_gen rst_gen{"rst_gen"};
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sc_core::sc_vector<tlm::scc::tlm_signal<sc_dt::sc_logic>> gpio_s{"gpio_s", 32};
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sc_core::sc_signal<bool> rst_n{"rst_n"};
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#ifndef WIN32 // Seasocks not available under windows
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vpvper::generic::terminal terminal{"terminal"};
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||||
#endif
|
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sc_core::sc_vector<sc_core::sc_signal<bool>> pins_o{"pins_o",32};
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||||
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_oe_o{"pins_oe_o", 32};
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||||
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_i{"pins_i", 32};
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||||
sc_core::sc_signal<bool> uart0_tx_o {"uart0_tx_o"};
|
||||
sc_core::sc_signal<bool> uart0_rx_i {"uart0_rx_i"};
|
||||
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
|
||||
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
|
||||
sc_core::sc_signal<bool> ssclk_o{"ssclk_o"};
|
||||
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_o{"dq_o", 4};
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||||
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_oe_o{"dq_oe_o", 4};
|
||||
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_i{"dq_i", 4};
|
||||
sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
|
||||
};
|
||||
|
||||
} /* namespace tgc_vp */
|
||||
|
|
|
|||
2
vpvper
2
vpvper
|
|
@ -1 +1 @@
|
|||
Subproject commit 2a3ec57906b8c5a1ab1cb146f214fe0b19aed564
|
||||
Subproject commit 899316db7ec527a46c968199a9c0e0f64e48fc2b
|
||||
Loading…
Reference in New Issue