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adds new mnrs vp modeled after ehrenberg

This commit is contained in:
Eyck-Alexander Jentzsch 2024-02-22 17:13:50 +01:00
parent 1c50084d9a
commit c12b00e52e
7 changed files with 131 additions and 148 deletions
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2
src/CMakeLists.txt
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@ -21,7 +21,7 @@ add_executable(${PROJECT_NAME}
) )
target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR}) target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR})
target_force_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc_sc) target_force_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc_sc)
target_link_libraries(${PROJECT_NAME} PUBLIC vpvper_generic vpvper_sifive ${BOOST_program_options_LIBRARY}) target_link_libraries(${PROJECT_NAME} PUBLIC vpvper_generic vpvper_minres ${BOOST_program_options_LIBRARY})
if(TARGET Boost::program_options) if(TARGET Boost::program_options)
target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread) target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
else() else()

17
test_gen/PipelinedMemoryBusToApbBridge.h → src/tgc_vp/gen/PipelinedMemoryBusToApbBridge.h
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@ -1,22 +1,21 @@
/* /*
* Copyright (c) 2023 MINRES Technologies GmbH * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Created on: «new Date» * Generated at 2024-02-08 14:41:56 UTC
* * «componentDefinition.effectiveName».h Author: <RDL Generator> * by peakrdl_mnrs version 1.2.2
*
*/ */
#pragma once #pragma once
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191 // need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<32>, 7> PipelinedMemoryBusToApbBridge_map = {{ const std::array<scc::target_memory_map_entry<scc::LT>, 6> PipelinedMemoryBusToApbBridge_map = {{
{ gpio0.socket, 0x0, 0xc }, { gpio0.socket, 0x0, 0xc },
{ uart0.socket, 0x1000, 0x14 }, { uart0.socket, 0x1000, 0x14 },
{ timer0.socket, 0x20000, 0x1c }, { timer0.socket, 0x20000, 0x1c },
{ aclint.socket, 0x30000, 0xc000 }, { aclint.socket, 0x30000, 0xc000 },
{ irq_ctrl.socket, 0x40000, 0x8 }, { irq_ctrl.socket, 0x40000, 0x8 },
{ qspi.socket, 0x50000, 0x5c }, { qspi.socket, 0x50000, 0x5c },
{ bootloader.socket, 0x80000, 0x400 }, //{ bootloader.socket, 0x80000, 0x400 },
}} ; }} ;

151
src/tgc_vp/system.cpp
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@ -5,124 +5,91 @@
*/ */
#include "tgc_vp/system.h" #include "tgc_vp/system.h"
#include "minres/timer.h"
#include "minres/uart.h"
#include "scc/utilities.h"
namespace tgc_vp { namespace tgc_vp {
using namespace sc_core; using namespace sc_core;
using namespace vpvper::sifive; using namespace vpvper::minres;
using namespace sysc::tgfs; using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm) system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm)
, NAMED(router, platfrom_mmap.size() + 2, 2) , NAMED(ahb_router, 3, 2)
{ , NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1){
core_complex.ibus(router.target[0]); core_complex.ibus(ahb_router.target[0]);
core_complex.dbus(router.target[1]); core_complex.dbus(ahb_router.target[1]);
ahb_router.initiator.at(0)(qspi.xip_sck);
ahb_router.set_target_range(0, 0xE0000000, 16_MB);
ahb_router.initiator.at(1)(mem_ram.target);
ahb_router.set_target_range(1, 0x80000000, 32_kB);
ahb_router.initiator.at(2)(apbBridge.target[0]);
ahb_router.set_target_range(2, 0xF0000000, 256_MB);
size_t i = 0; size_t i = 0;
for (const auto &e : platfrom_mmap) { for (const auto &e : PipelinedMemoryBusToApbBridge_map) {
router.initiator.at(i)(e.target); apbBridge.initiator.at(i)(e.target);
router.set_target_range(i, e.start, e.size); apbBridge.set_target_range(i, e.start, e.size);
i++; i++;
} }
router.initiator.at(i)(mem_qspi.target);
router.set_target_range(i, 0x20000000, 512_MB);
router.initiator.at(++i)(mem_ram.target);
router.set_target_range(i, 0x80000000, 128_kB);
uart1.clk_i(tlclk_s); gpio0.clk_i(clk_i);
qspi0.clk_i(tlclk_s); uart0.clk_i(clk_i);
qspi1.clk_i(tlclk_s); timer0.clk_i(clk_i);
qspi2.clk_i(tlclk_s); aclint.clk_i(clk_i);
pwm0.clk_i(tlclk_s); irq_ctrl.clk_i(clk_i);
pwm1.clk_i(tlclk_s); qspi.clk_i(clk_i);
pwm2.clk_i(tlclk_s); core_complex.clk_i(clk_i);
gpio0.clk_i(tlclk_s); //mem_ram.clk_i(clk_i);
plic.clk_i(tlclk_s);
aon.clk_i(tlclk_s);
aon.lfclkc_o(lfclk_s);
prci.hfclk_o(tlclk_s); // clock driver
clint.tlclk_i(tlclk_s);
clint.lfclk_i(lfclk_s);
core_complex.clk_i(tlclk_s);
mem_qspi.clk_i(tlclk_s);
mem_ram.clk_i(tlclk_s);
uart0.rst_i(rst_s);
uart1.rst_i(rst_s);
qspi0.rst_i(rst_s);
qspi1.rst_i(rst_s);
qspi2.rst_i(rst_s);
pwm0.rst_i(rst_s);
pwm1.rst_i(rst_s);
pwm2.rst_i(rst_s);
gpio0.rst_i(rst_s); gpio0.rst_i(rst_s);
plic.rst_i(rst_s); uart0.rst_i(rst_s);
aon.rst_o(rst_s); timer0.rst_i(rst_s);
prci.rst_i(rst_s); aclint.rst_i(rst_s);
clint.rst_i(rst_s); irq_ctrl.rst_i(rst_s);
qspi.rst_i(rst_s);
core_complex.rst_i(rst_s); core_complex.rst_i(rst_s);
aon.erst_n_i(erst_n); aclint.mtime_int_o(mtime_int_s);
aclint.msip_int_o(msip_int_s);
irq_ctrl.irq_o(core_int_s);
irq_ctrl.pending_irq_i(irq_int_s);
clint.mtime_int_o(mtime_int_s); uart0.irq_o(irq_int_s[0]);
clint.msip_int_o(msie_int_s); timer0.interrupt_o[0](irq_int_s[1]);
timer0.interrupt_o[1](irq_int_s[2]);
qspi.irq_o(irq_int_s[3]);
plic.global_interrupts_i(global_int_s);
plic.core_interrupt_o(core_int_s);
core_complex.sw_irq_i(msie_int_s);
core_complex.timer_irq_i(mtime_int_s); core_complex.timer_irq_i(mtime_int_s);
core_complex.ext_irq_i(core_int_s); core_complex.ext_irq_i(core_int_s);
core_complex.local_irq_i(local_int_s); core_complex.local_irq_i(local_int_s);
core_complex.sw_irq_i(msip_int_s);
pins_i(gpio0.pins_i); gpio0.pins_i(pins_i);
gpio0.pins_o(pins_o); gpio0.pins_o(pins_o);
gpio0.oe_o(pins_oe_o);
uart0.irq_o(global_int_s[3]); uart0.tx_o(uart0_tx_o);
uart0.rx_i(uart0_rx_i);
gpio0.iof0_i[5](qspi1.sck_o); timer0.clear_i(t0_clear_i);
gpio0.iof0_i[3](qspi1.mosi_o); timer0.tick_i(t0_tick_i);
qspi1.miso_i(gpio0.iof0_o[4]);
gpio0.iof0_i[2](qspi1.scs_o[0]);
gpio0.iof0_i[9](qspi1.scs_o[2]);
gpio0.iof0_i[10](qspi1.scs_o[3]);
qspi0.irq_o(global_int_s[5]); qspi.ssclk_o(ssclk_o);
qspi1.irq_o(global_int_s[6]); qspi.dq_o(dq_o);
qspi2.irq_o(global_int_s[7]); qspi.dq_i(dq_i);
qspi.oe_o(dq_oe_o);
gpio0.iof0_i[16](uart1.tx_o); SC_METHOD(gen_reset);
uart1.rx_i(gpio0.iof0_o[17]); sensitive << erst_n;
uart1.irq_o(global_int_s[4]); }
void system::gen_reset(){
gpio0.iof1_i[0](pwm0.cmpgpio_o[0]); if(erst_n.read())
gpio0.iof1_i[1](pwm0.cmpgpio_o[1]); rst_s = 0;
gpio0.iof1_i[2](pwm0.cmpgpio_o[2]); else rst_s = 1;
gpio0.iof1_i[3](pwm0.cmpgpio_o[3]);
gpio0.iof1_i[10](pwm2.cmpgpio_o[0]);
gpio0.iof1_i[11](pwm2.cmpgpio_o[1]);
gpio0.iof1_i[12](pwm2.cmpgpio_o[2]);
gpio0.iof1_i[13](pwm2.cmpgpio_o[3]);
gpio0.iof1_i[19](pwm1.cmpgpio_o[0]);
gpio0.iof1_i[20](pwm1.cmpgpio_o[1]);
gpio0.iof1_i[21](pwm1.cmpgpio_o[2]);
gpio0.iof1_i[22](pwm1.cmpgpio_o[3]);
pwm0.cmpip_o[0](global_int_s[40]);
pwm0.cmpip_o[1](global_int_s[41]);
pwm0.cmpip_o[2](global_int_s[42]);
pwm0.cmpip_o[3](global_int_s[43]);
pwm1.cmpip_o[0](global_int_s[44]);
pwm1.cmpip_o[1](global_int_s[45]);
pwm1.cmpip_o[2](global_int_s[46]);
pwm1.cmpip_o[3](global_int_s[47]);
pwm2.cmpip_o[0](global_int_s[48]);
pwm2.cmpip_o[1](global_int_s[49]);
pwm2.cmpip_o[2](global_int_s[50]);
pwm2.cmpip_o[3](global_int_s[51]);
} }
} /* namespace sysc */ } /* namespace sysc */

68
src/tgc_vp/system.h
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@ -7,20 +7,21 @@
#ifndef _PLATFORM_H_ #ifndef _PLATFORM_H_
#define _PLATFORM_H_ #define _PLATFORM_H_
#include <sifive/aon.h> #include "minres/irq.h"
#include <sifive/clint.h> #include "minres/timer.h"
#include <sifive/gpio.h> #include <minres/aclint.h>
#include <sifive/plic.h> #include <minres/gpio.h>
#include <sifive/prci.h> #include <minres/qspi.h>
#include <sifive/pwm.h> #include <sysc/communication/sc_clock.h>
#include <sifive/spi.h> #include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h> #include <sysc/core_complex.h>
#include <sifive/uart.h> #include <minres/uart.h>
#include <sifive/uart_terminal.h>
#include <cci_configuration> #include <cci_configuration>
#include <scc/memory.h> #include <scc/memory.h>
#include <scc/router.h> #include <scc/router.h>
#include <scc/utilities.h> #include <scc/utilities.h>
#include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h>
#include <tlm/scc/tlm_signal_sockets.h> #include <tlm/scc/tlm_signal_sockets.h>
#include <array> #include <array>
#include <memory> #include <memory>
@ -32,8 +33,19 @@ class system : public sc_core::sc_module {
public: public:
SC_HAS_PROCESS(system);// NOLINT SC_HAS_PROCESS(system);// NOLINT
sc_core::sc_vector<tlm::scc::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o{"pins_o", 32}; sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o",32};
sc_core::sc_vector<tlm::scc::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i{"pins_i", 32}; sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
sc_core::sc_out<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_in<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_out<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_oe_o{"dq_oe_o", 4};
sc_core::sc_vector<sc_core::sc_in<bool>> dq_i{"dq_i", 4};
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
sc_core::sc_in<bool> erst_n{"erst_n"}; sc_core::sc_in<bool> erst_n{"erst_n"};
@ -41,32 +53,24 @@ public:
private: private:
sysc::tgfs::core_complex core_complex{"core_complex"}; sysc::tgfs::core_complex core_complex{"core_complex"};
scc::router<> router; scc::router<> ahb_router, apbBridge;
vpvper::sifive::uart_terminal uart0{"uart0"}; vpvper::minres::gpio_tl gpio0{"gpio0"};
vpvper::sifive::uart uart1{"uart1"}; vpvper::minres::uart_tl uart0{"uart0"};
vpvper::sifive::spi qspi0{"qspi0"}, qspi1{"qspi1"}, qspi2{"qspi2"}; vpvper::minres::timer_tl timer0{"timer0"};
vpvper::sifive::pwm pwm0{"pwm0"}, pwm1{"pwm1"}, pwm2{"pwm2"}; vpvper::minres::aclint_tl aclint{"aclint"};
vpvper::sifive::gpio gpio0{"gpio0"}; vpvper::minres::irq_tl irq_ctrl{"irq_ctrl"};
vpvper::sifive::plic plic{"plic"}; vpvper::minres::qspi_tl qspi{"qspi"};
vpvper::sifive::aon aon{"aon"};
vpvper::sifive::prci prci{"prci"};
vpvper::sifive::clint clint{"clint"};
using mem_qspi_t = scc::memory<512_MB, scc::LT>; //scc::memory<1_kB, scc::LT> bootloader{"bootloader"};
mem_qspi_t mem_qspi{"mem_qspi"}; scc::memory<32_kB, scc::LT> mem_ram {"mem_ram"};
using mem_ram_t = scc::memory<128_kB, scc::LT>;
mem_ram_t mem_ram{"mem_ram"}; sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"};
sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> tlclk_s{"tlclk_s"};
sc_core::sc_signal<sc_core::sc_time, sc_core::SC_MANY_WRITERS> lfclk_s{"lfclk_s"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msie_int_s{"msie_int_s"}; sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> global_int_s{"global_int_s", 256}, local_int_s{"local_int_s", 16};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"}; sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
void gen_reset(); void gen_reset();
#include "tgc_vp/gen/platform_mmap.h" #include "tgc_vp/gen/PipelinedMemoryBusToApbBridge.h"
}; };
} /* namespace sysc */ } /* namespace sysc */

23
src/tgc_vp/tb.cpp
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@ -5,20 +5,25 @@
*/ */
#include "tgc_vp/tb.h" #include "tgc_vp/tb.h"
#include <sysc/kernel/sc_time.h>
namespace tgc_vp { namespace tgc_vp {
SC_HAS_PROCESS(tb); SC_HAS_PROCESS(tb);
tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) { tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
top.erst_n(rst_n); top.erst_n(rst_n);
rst_gen.rst_n(rst_n); rst_gen.rst_n(rst_n);
for (auto i = 0U; i < gpio_s.size(); ++i) { top.pins_o(pins_o);
gpio_s[i].in(top.pins_o[i]); top.pins_i(pins_i);
top.pins_i[i](gpio_s[i].out); top.pins_oe_o(pins_oe_o);
} top.uart0_rx_i(uart0_rx_i);
#ifndef WIN32 top.uart0_tx_o(uart0_tx_o);
// terminal top.t0_clear_i(t0_clear_i);
terminal.tx_o(gpio_s[16].in); top.t0_tick_i(t0_tick_i);
gpio_s[17].out(terminal.rx_i); top.ssclk_o(ssclk_o);
#endif top.dq_o(dq_o);
top.dq_i(dq_i);
top.dq_oe_o(dq_oe_o);
top.clk_i(clk_i);
clk_i = 10_ns;
} }
} }

16
src/tgc_vp/tb.h
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@ -19,11 +19,19 @@ public:
tb(sc_core::sc_module_name const& nm); tb(sc_core::sc_module_name const& nm);
tgc_vp::system top{"top"}; tgc_vp::system top{"top"};
tgc_vp::rst_gen rst_gen{"rst_gen"}; tgc_vp::rst_gen rst_gen{"rst_gen"};
sc_core::sc_vector<tlm::scc::tlm_signal<sc_dt::sc_logic>> gpio_s{"gpio_s", 32};
sc_core::sc_signal<bool> rst_n{"rst_n"}; sc_core::sc_signal<bool> rst_n{"rst_n"};
#ifndef WIN32 // Seasocks not available under windows sc_core::sc_vector<sc_core::sc_signal<bool>> pins_o{"pins_o",32};
vpvper::generic::terminal terminal{"terminal"}; sc_core::sc_vector<sc_core::sc_signal<bool>> pins_oe_o{"pins_oe_o", 32};
#endif sc_core::sc_vector<sc_core::sc_signal<bool>> pins_i{"pins_i", 32};
sc_core::sc_signal<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_signal<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_signal<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_oe_o{"dq_oe_o", 4};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_i{"dq_i", 4};
sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
}; };
} /* namespace tgc_vp */ } /* namespace tgc_vp */

2
vpvper

@ -1 +1 @@
Subproject commit 2a3ec57906b8c5a1ab1cb146f214fe0b19aed564 Subproject commit 899316db7ec527a46c968199a9c0e0f64e48fc2b