adds bsp as submodule

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "tgc-iss/dbt-rise-tgc"]
 	path = tgc-iss/dbt-rise-tgc
 	url = https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git
+[submodule "fw/bsp"]
+	path = fw/bsp
+	url = https://git.minres.com/Firmware/MNRS-BM-BSP.git

fw/hello-world/.gitignore

@@ -1,3 +1,3 @@
 /hello
 /hello.dis
-/firmware.map
+/hello.map

fw/hello-world/Makefile

@@ -1,17 +1,28 @@
 
 TARGET  = hello
+ISA?=imc
+
 C_SRCS  = $(wildcard *.c) 
 HEADERS = $(wildcard *.h)
-CFLAGS += -O0 -g 
+OPT ?= -O2
+CFLAGS += $(OPT) -g 
 
-BOARD=tgfs-vp
+BOARD=tgc_vp
-LINK_TARGET=flash
+LINK_TARGET=link
-RISCV_ARCH:=rv32i
+RISCV_ARCH:=rv32$(ISA)
-RISCV_ABI:=ilp32
+ifeq ($(ISA),e)
-LDFLAGS := -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
+    RISCV_ABI:=ilp32e
+else
+    RISCV_ABI:=ilp32
+endif
+LDFLAGS += -g -Wl,--wrap=printf
 
-compiler := $(shell which riscv32-unknown-elf-gcc)
+compiler := $(shell which riscv64-unknown-elf-gcc)
 TOOL_DIR=$(dir $(compiler))
 
+TRIPLET=riscv64-unknown-elf
 BSP_BASE = ../bsp
 include $(BSP_BASE)/env/common-gcc.mk
+
+$(TARGET).vlog:$(TARGET)
+	riscv32-unknown-elf-objcopy -O verilog $(TARGET) $(TARGET).vlog

fw/hello-world/hello.c

@@ -17,8 +17,6 @@ int factorial(int i){
 
 int main()
 {
-    *(uint32_t*)(GPIO_CTRL_ADDR+GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
-    *(uint32_t*)(GPIO_CTRL_ADDR+GPIO_IOF_EN)  |= IOF0_UART0_MASK;
 	volatile int result = factorial (10);
 	printf("Factorial is %d\n", result);
 	printf("End of execution");