VP/TGC-VP
7
0
Fork 0
Code Issues Pull Requests Projects Releases Activity

applies clang-format (incl. submodules), adds launch configs

Browse Source
This commit is contained in:
Eyck Jentzsch
2024-08-17 16:19:10 +02:00
parent f122b0ae4e
commit 61d8d3c661
25 changed files with 347 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
src/tgc_vp/gen/PipelinedMemoryBusToApbBridge.h
View File

@@ -1,21 +1,21 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-08 14:41:56 UTC
* by peakrdl_mnrs version 1.2.2
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-08 14:41:56 UTC
* by peakrdl_mnrs version 1.2.2
*/
#pragma once
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<scc::LT>, 7> PipelinedMemoryBusToApbBridge_map = {{
{ gpio0.socket, 0x0, 0xc },
{ uart0.socket, 0x1000, 0x14 },
{ timer0.socket, 0x20000, 0x1c },
{ aclint.socket, 0x30000, 0xc000 },
{ irq_ctrl.socket, 0x40000, 0x8 },
{ qspi.socket, 0x50000, 0x5c },
{ boot_rom.target, 0x80000, 0x5c }
}} ;
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<scc::LT>, 7> PipelinedMemoryBusToApbBridge_map = {
{{gpio0.socket, 0x0, 0xc},
{uart0.socket, 0x1000, 0x14},
{timer0.socket, 0x20000, 0x1c},
{aclint.socket, 0x30000, 0xc000},
{irq_ctrl.socket, 0x40000, 0x8},
{qspi.socket, 0x50000, 0x5c},
{boot_rom.target, 0x80000, 0x5c}}};

8
src/tgc_vp/rst_gen.h
View File

@@ -11,13 +11,13 @@ namespace tgc_vp {
class rst_gen : public sc_core::sc_module {
SC_HAS_PROCESS(rst_gen);
public:
rst_gen(sc_core::sc_module_name const& nm) {
SC_THREAD(run);
}
rst_gen(sc_core::sc_module_name const& nm) { SC_THREAD(run); }
sc_core::sc_out<bool> rst_n{"rst_n"};
private:
void run(){
void run() {
rst_n.write(false);
wait(100_ns);
rst_n.write(true);

11
src/tgc_vp/system.cpp
View File

@@ -17,7 +17,7 @@ using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(ahb_router, 3, 2)
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1){
, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
core_complex.ibus(ahb_router.target[0]);
core_complex.dbus(ahb_router.target[1]);
@@ -29,7 +29,7 @@ system::system(sc_core::sc_module_name nm)
ahb_router.set_target_range(2, 0xF0000000, 256_MB);
size_t i = 0;
for (const auto &e : PipelinedMemoryBusToApbBridge_map) {
for(const auto& e : PipelinedMemoryBusToApbBridge_map) {
apbBridge.initiator.at(i)(e.target);
apbBridge.set_target_range(i, e.start, e.size);
i++;
@@ -86,9 +86,6 @@ system::system(sc_core::sc_module_name nm)
SC_METHOD(gen_reset);
sensitive << erst_n;
}
void system::gen_reset(){
rst_s = !erst_n.read();
}
void system::gen_reset() { rst_s = !erst_n.read(); }
} /* namespace sysc */
} // namespace tgc_vp

46
src/tgc_vp/system.h
View File

@@ -9,42 +9,42 @@
#include "minres/irq.h"
#include "minres/timer.h"
#include <array>
#include <cci_configuration>
#include <memory>
#include <minres/aclint.h>
#include <minres/gpio.h>
#include <minres/qspi.h>
#include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h>
#include <minres/uart.h>
#include <cci_configuration>
#include <scc/memory.h>
#include <scc/router.h>
#include <scc/utilities.h>
#include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h>
#include <sysc/kernel/sc_module.h>
#include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h>
#include <tlm/scc/tlm_signal_sockets.h>
#include <array>
#include <memory>
#include <sysc/kernel/sc_module.h>
namespace tgc_vp {
class system : public sc_core::sc_module {
public:
SC_HAS_PROCESS(system);// NOLINT
SC_HAS_PROCESS(system); // NOLINT
sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o",32};
sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o", 32};
sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
sc_core::sc_out<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_in<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
sc_core::sc_out<bool> uart0_tx_o{"uart0_tx_o"};
sc_core::sc_in<bool> uart0_rx_i{"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
sc_core::sc_out<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_out<bool>> dq_oe_o{"dq_oe_o", 4};
sc_core::sc_vector<sc_core::sc_in<bool>> dq_i{"dq_i", 4};
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
sc_core::sc_in<bool> erst_n{"erst_n"};
@@ -62,17 +62,19 @@ private:
vpvper::minres::qspi_tl qspi{"qspi"};
scc::memory<1_kB, scc::LT> boot_rom{"boot_rom"};
scc::memory<32_kB, scc::LT> main_ram {"main_ram"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"}, msip_int_s{"msip_int_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32}, local_int_s{"local_int_s", 16};
scc::memory<32_kB, scc::LT> main_ram{"main_ram"};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"}, mtime_int_s{"mtime_int_s"},
msip_int_s{"msip_int_s"};
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32},
local_int_s{"local_int_s", 16};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
void gen_reset();
#include "tgc_vp/gen/PipelinedMemoryBusToApbBridge.h"
};
} /* namespace sysc */
} // namespace tgc_vp
#endif /* _PLATFORM_H_ */

5
src/tgc_vp/tb.cpp
View File

@@ -9,7 +9,8 @@
namespace tgc_vp {
SC_HAS_PROCESS(tb);
tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
tb::tb(const sc_core::sc_module_name& nm)
: sc_core::sc_module(nm) {
top.erst_n(rst_n);
rst_gen.rst_n(rst_n);
top.pins_o(pins_o);
@@ -26,4 +27,4 @@ tb::tb(const sc_core::sc_module_name &nm): sc_core::sc_module(nm) {
top.clk_i(clk_i);
clk_i = 10_ns;
}
}
} // namespace tgc_vp

12
src/tgc_vp/tb.h
View File

@@ -20,13 +20,13 @@ public:
tgc_vp::system top{"top"};
tgc_vp::rst_gen rst_gen{"rst_gen"};
sc_core::sc_signal<bool> rst_n{"rst_n"};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_o{"pins_o",32};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_o{"pins_o", 32};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_oe_o{"pins_oe_o", 32};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_i{"pins_i", 32};
sc_core::sc_signal<bool> uart0_tx_o {"uart0_tx_o"};
sc_core::sc_signal<bool> uart0_rx_i {"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i {"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i {"t0_tick_i", vpvper::minres::timer::TICK_CNT-1};
sc_core::sc_vector<sc_core::sc_signal<bool>> pins_i{"pins_i", 32};
sc_core::sc_signal<bool> uart0_tx_o{"uart0_tx_o"};
sc_core::sc_signal<bool> uart0_rx_i{"uart0_rx_i"};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
sc_core::sc_signal<bool> ssclk_o{"ssclk_o"};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_o{"dq_o", 4};
sc_core::sc_vector<sc_core::sc_signal<bool>> dq_oe_o{"dq_oe_o", 4};