405 lines
18 KiB
Plaintext
405 lines
18 KiB
Plaintext
import "RV32IBase.core_desc"
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InsructionSet RV32F extends RV32IBase{
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constants {
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FLEN, FFLAG_MASK := 0x1f
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}
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registers {
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[31:0] F[FLEN], FCSR[32]
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}
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instructions{
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FLW {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
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args_disass:"f{rd}, {imm}(x{rs1})";
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val offs[XLEN] <= X[rs1]'s + imm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSW {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
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args_disass:"f{rs2}, {imm}(x{rs1})";
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val offs[XLEN] <= X[rs1]'s + imm;
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MEM[offs]{32}<=F[rs2]{32};
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}
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FMADD.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
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args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val frs3[32] <= fdispatch_unbox_s(F[rs3]);
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val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMSUB.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
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args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val frs3[32] <= fdispatch_unbox_s(F[rs3]);
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val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMADD.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
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args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val frs3[32] <= fdispatch_unbox_s(F[rs3]);
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val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMSUB.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
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args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val frs3[32] <= fdispatch_unbox_s(F[rs3]);
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val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FADD.S {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f + F[rs2]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fadd_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fadd_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSUB.S {
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encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f - F[rs2]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fsub_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fsub_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMUL.S {
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encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f * F[rs2]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fmul_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fmul_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FDIV.S {
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encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f / F[rs2]f;
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if(FLEN==32)
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F[rd] <= fdispatch_fdiv_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fdiv_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSQRT.S {
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encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}";
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//F[rd]f<=sqrt(F[rs1]f);
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if(FLEN==32)
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F[rd] <= fdispatch_fsqrt_s(F[rs1], choose(rm<7, rm{8}, FCSR{8}));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val res[32] <= fdispatch_fsqrt_s(frs1, choose(rm<7, rm{8}, FCSR{8}));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSGNJ.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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if(FLEN==32)
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F[rd] <= (F[rs1] & 0x7fffffff) | (F[rs2] & 0x80000000);
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= (frs1 & 0x7fffffff) | (frs2 & 0x80000000);
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSGNJN.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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if(FLEN==32)
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F[rd] <= (F[rs1] & 0x7fffffff) | (~F[rs2] & 0x80000000);
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= (frs1 & 0x7fffffff) | (~frs2 & 0x80000000);
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSGNJX.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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if(FLEN==32)
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F[rd] <= F[rs1] ^ (F[rs2] & 0x80000000);
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= frs1 ^ (frs2 & 0x80000000);
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FMIN.S {
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encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
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if(FLEN==32)
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F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(0, 32));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(0, 32));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMAX.S {
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encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
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if(FLEN==32)
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F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(1, 32));
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(1, 32));
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.W.S {
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encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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if(FLEN==32)
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X[rd] <= sext(fdispatch_fcvt_s(F[rs1], zext(0, 32), rm{8}), XLEN);
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(0, 32), rm{8}), XLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.WU.S {
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encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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//FIXME: according to the spec it should be zero-extended not sign extended
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if(FLEN==32)
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X[rd]<= sext(fdispatch_fcvt_s(F[rs1], zext(1, 32), rm{8}), XLEN);
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else { // NaN boxing
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(1, 32), rm{8}), XLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FEQ.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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if(FLEN==32)
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X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(0, 32)));
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else {
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(0, 32)));
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLT.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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if(FLEN==32)
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X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(2, 32)));
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else {
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(2, 32)));
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}
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X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLE.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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if(FLEN==32)
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X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(1, 32)));
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else {
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val frs1[32] <= fdispatch_unbox_s(F[rs1]);
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val frs2[32] <= fdispatch_unbox_s(F[rs2]);
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X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(1, 32)));
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCLASS.S {
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encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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X[rd]<=fdispatch_fclass_s(fdispatch_unbox_s(F[rs1]));
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}
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FCVT.S.W {
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encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, {name(rs1)}";
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if(FLEN==32)
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F[rd] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
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else { // NaN boxing
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val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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|
}
|
|
FCVT.S.WU {
|
|
encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
|
args_disass:"f{rd}, {name(rs1)}";
|
|
if(FLEN==32)
|
|
F[rd] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
|
|
else { // NaN boxing
|
|
val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
|
|
val upper[FLEN] <= -1;
|
|
F[rd] <= (upper<<32) | zext(res, FLEN);
|
|
}
|
|
}
|
|
FMV.X.W {
|
|
encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
|
args_disass:"{name(rd)}, f{rs1}";
|
|
X[rd]<=sext(F[rs1]{32});
|
|
}
|
|
FMV.W.X {
|
|
encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
|
args_disass:"f{rd}, {name(rs1)}";
|
|
if(FLEN==32)
|
|
F[rd] <= X[rs1]{32};
|
|
else { // NaN boxing
|
|
val upper[FLEN] <= -1;
|
|
F[rd] <= (upper<<32) | zext(X[rs1]{32}, FLEN);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
InsructionSet RV64F extends RV32F{
|
|
constants {
|
|
FLEN, FFLAG_MASK := 0x1f
|
|
}
|
|
registers {
|
|
[31:0] F[FLEN], FCSR[32]
|
|
}
|
|
instructions{
|
|
FCVT.L.S { // fp to 64bit signed integer
|
|
encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
|
args_disass:"x{rd}, f{rs1}";
|
|
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(0, 32), rm{8});
|
|
X[rd]<= sext(res);
|
|
val flags[32] <= fdispatch_fget_flags();
|
|
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
|
|
}
|
|
FCVT.LU.S { // fp to 64bit unsigned integer
|
|
encoding: b1100000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
|
args_disass:"x{rd}, f{rs1}";
|
|
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(1, 32), rm{8});
|
|
X[rd]<= zext(res);
|
|
val flags[32] <= fdispatch_fget_flags();
|
|
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
|
|
}
|
|
FCVT.S.L { // 64bit signed int to to fp
|
|
encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
|
args_disass:"f{rd}, x{rs1}";
|
|
val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32));
|
|
if(FLEN==32)
|
|
F[rd] <= res;
|
|
else { // NaN boxing
|
|
val upper[FLEN] <= -1;
|
|
F[rd] <= (upper<<32) | zext(res, FLEN);
|
|
}
|
|
}
|
|
FCVT.S.LU { // 64bit unsigned int to to fp
|
|
encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
|
args_disass:"f{rd}, x{rs1}";
|
|
val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32));
|
|
if(FLEN==32)
|
|
F[rd] <= res;
|
|
else { // NaN boxing
|
|
val upper[FLEN] <= -1;
|
|
F[rd] <= (upper<<32) | zext(res, FLEN);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|