104 lines
4.5 KiB
Plaintext
104 lines
4.5 KiB
Plaintext
import "RV32IBase.core_desc"
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InsructionSet RV32A extends RV32IBase{
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instructions{
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LR.W {
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encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}";
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if(rd!=0){
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val offs[XLEN] <= X[rs1];
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X[rd]<= sext(MEM[offs]{32}, XLEN);
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RES[offs]{32}<=sext(-1, 32);
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}
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}
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SC.W {
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encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
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val offs[XLEN] <= X[rs1];
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val res1[32] <= RES[offs]{32};
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if(res1!=0)
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MEM[offs]{32} <= X[rs2];
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if(rd!=0) X[rd]<= choose(res1!=zext(0, 32), 0, 1);
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}
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AMOSWAP.W{
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encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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if(rd!=0) X[rd]<=sext(MEM[offs]{32});
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MEM[offs]{32}<=X[rs2];
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}
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AMOADD.W{
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encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN]<=res1 + X[rs2];
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MEM[offs]{32}<=res2;
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}
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AMOXOR.W{
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encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN]<=res1 ^ X[rs2];
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MEM[offs]{32}<=res2;
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}
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AMOAND.W{
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encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN] <=res1 & X[rs2];
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MEM[offs]{32}<=res2;
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}
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AMOOR.W {
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encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN]<=res1 | X[rs2];
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MEM[offs]{32}<=res2;
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}
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AMOMIN.W{
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encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd] <= res1;
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val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
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MEM[offs]{32} <= res2;
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}
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AMOMAX.W{
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encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
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MEM[offs]{32}<=res2;
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}
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AMOMINU.W{
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encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd]<=res1;
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val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
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MEM[offs]{32}<=res2;
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}
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AMOMAXU.W{
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encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
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args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
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val offs[XLEN]<=X[rs1];
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val res1[XLEN] <= sext(MEM[offs]{32});
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if(rd!=0) X[rd] <= res1;
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val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
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MEM[offs]{32} <= res2;
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}
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}
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} |