96 lines
3.2 KiB
C++
96 lines
3.2 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "sysc/SiFive/prci.h"
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#include "scc/utilities.h"
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#include "sysc/SiFive/gen/prci_regs.h"
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namespace sysc {
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prci::prci(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMEDD(prci_regs, regs) {
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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SC_METHOD(hfrosc_en_cb);
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sensitive << hfrosc_en_evt;
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dont_initialize();
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regs->hfrosccfg.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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reg.put(data);
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if (this->regs->r_hfrosccfg & (1 << 30)) { // check rosc_en
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this->hfrosc_en_evt.notify(1, sc_core::SC_US);
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}
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return true;
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});
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regs->pllcfg.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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reg.put(data);
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auto &pllcfg = this->regs->r_pllcfg;
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if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected
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pllcfg.plllock = 1;
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}
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return true;
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});
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}
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void prci::clock_cb() {
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this->clk = clk_i.read();
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}
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prci::~prci() {}
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void prci::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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void prci::hfrosc_en_cb() {
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regs->r_hfrosccfg |= (1 << 31); // set rosc_rdy
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}
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} /* namespace sysc */
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