50 lines
1.4 KiB
Plaintext
50 lines
1.4 KiB
Plaintext
import "RV32IBase.core_desc"
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import "RV32M.core_desc"
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import "RV32A.core_desc"
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import "RV32C.core_desc"
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import "RV32F.core_desc"
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import "RV32D.core_desc"
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import "RV64IBase.core_desc"
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//import "RV64M.core_desc"
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import "RV64A.core_desc"
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Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
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template:"vm_riscv.in.cpp";
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32DC {
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constants {
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XLEN:=32;
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FLEN:=64;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64IA provides RV64IBase, RV64A, RV32A {
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template:"vm_riscv.in.cpp";
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constants {
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XLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000001;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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