294 lines
9.6 KiB
Plaintext
294 lines
9.6 KiB
Plaintext
import "RV32IBase.core_desc"
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InsructionSet RV32F extends RV32IBase{
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constants {
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FLEN, FFLAG_MASK
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}
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registers {
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[31:0] F[FLEN], FCSR[32]
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}
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instructions{
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FLW {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
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args_disass:"f%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSW {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
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args_disass:"f%rs2$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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MEM[offs]{32}<=F[rs2]{32};
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}
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FMADD.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
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//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
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val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMSUB.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
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//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
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val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMADD.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
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//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
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val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMSUB.S {
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encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
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//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
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val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FADD.S {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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// F[rd]f <= F[rs1]f + F[rs2]f;
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val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSUB.S {
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encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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// F[rd]f <= F[rs1]f - F[rs2]f;
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val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMUL.S {
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encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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// F[rd]f <= F[rs1]f * F[rs2]f;
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val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FDIV.S {
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encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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// F[rd]f <= F[rs1]f / F[rs2]f;
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val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSQRT.S {
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encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d";
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//F[rd]f<=sqrt(F[rs1]f);
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val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSGNJ.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSGNJN.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FSGNJX.S {
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encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FMIN.S {
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encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
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val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMAX.S {
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encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
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//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
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val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.W.S {
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encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d";
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X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.WU.S {
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encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d";
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X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FEQ.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
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X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLT.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
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X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLE.S {
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encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
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X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCLASS.S {
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encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d";
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X[rd]<=fdispatch_fclass_s(F[rs1]{32});
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}
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FCVT.S.W {
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encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, x%rs1$d";
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val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FCVT.S.WU {
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encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f%rd$d, x%rs1$d";
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val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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FMV.X.W {
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encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"x%rd$d, f%rs1$d";
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X[rd]<=sext(F[rs1]{32});
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}
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FMV.W.X {
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encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f%rd$d, x%rs1$d";
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if(FLEN==32)
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F[rd] <= X[rs1];
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(X[rs1], FLEN);
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}
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}
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}
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} |