368 lines
14 KiB
Plaintext
368 lines
14 KiB
Plaintext
import "RISCVBase.core_desc"
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InsructionSet RV32IC extends RISCVBase{
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instructions{
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JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
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args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
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val new_pc[XLEN] <= X[rs1]s + imm;
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if(rd!=0) X[rd] <= PC+4;
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PC<=new_pc & ~0x1;
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}
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C.ADDI4SPN { //(RES, imm=0)
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encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
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args_disass: "{name(rd)}, {imm:#05x}";
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if(imm == 0) raise(0, 2);
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X[rd+8] <= X[2] + imm;
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}
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C.LW { // (RV32)
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encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
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args_disass: "{name(8+rd)}, {uimm:#05x}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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X[rd+8] <= sext(MEM[offs]{32});
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}
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C.SW {//(RV32)
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encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
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args_disass: "{name(8+rs2)}, {uimm:#05x}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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MEM[offs]{32} <= X[rs2+8];
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}
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C.ADDI {//(RV32)
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encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
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args_disass: "{name(rs1)}, {imm:#05x}";
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X[rs1] <= X[rs1]'s + imm;
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}
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C.NOP {
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encoding:b000 | b0 | b00000 | b00000 | b01;
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}
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// C.JAL will be overwritten by C.ADDIW for RV64/128
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C.JAL(no_cont) {//(RV32)
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encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
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args_disass: "{imm:#05x}";
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X[1] <= PC+2;
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PC<=PC's+imm;
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}
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C.LI {//(RV32)
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encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
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args_disass: "{name(rd)}, {imm:#05x}";
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if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
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X[rd] <= imm;
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}
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// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
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C.LUI {//(RV32)
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encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01;
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args_disass: "{name(rd)}, {imm:#05x}";
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if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
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if(imm == 0) raise(0, 2); //TODO: should it be handled as trap?
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X[rd] <= imm;
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}
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C.ADDI16SP {//(RV32)
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encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
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args_disass: "{imm:#05x}";
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X[2] <= X[2]s + imm;
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}
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C.SRLI {//(RV32 nse)
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encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shrl(X[rs1_idx], shamt);
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}
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C.SRAI {//(RV32)
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encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shra(X[rs1_idx], shamt);
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}
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C.ANDI {//(RV32)
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encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
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args_disass: "{name(8+rs1)}, {imm:#05x}";
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val rs1_idx[5] <= rs1 + 8;
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X[rs1_idx] <= X[rs1_idx]s & imm;
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}
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C.SUB {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rs2)}";
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val rd_idx[5] <= rd + 8;
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X[rd_idx] <= X[rd_idx] - X[rs2 + 8];
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}
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C.XOR {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rs2)}";
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val rd_idx[5] <= rd + 8;
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X[rd_idx] <= X[rd_idx] ^ X[rs2 + 8];
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}
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C.OR {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rs2)}";
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val rd_idx[5] <= rd + 8;
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X[rd_idx] <= X[rd_idx] | X[rs2 + 8];
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}
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C.AND {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rs2)}";
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val rd_idx[5] <= rd + 8;
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X[rd_idx] <= X[rd_idx] & X[rs2 + 8];
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}
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C.J(no_cont) {//(RV32)
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encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
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args_disass: "{imm:#05x}";
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PC<=PC's+imm;
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}
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C.BEQZ(no_cont,cond) {//(RV32)
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encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
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args_disass: "{name(8+rs1)}, {imm:#05x}";
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PC<=choose(X[rs1+8]==0, PC's+imm, PC+2);
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}
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C.BNEZ(no_cont,cond) {//(RV32)
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encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
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args_disass: "{name(8+rs1)}, {imm:#05x}";
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PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2);
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}
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C.SLLI {//(RV32)
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encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
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args_disass: "{name(rs1)}, {shamt}";
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if(rs1 == 0) raise(0, 2);
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X[rs1] <= shll(X[rs1], shamt);
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}
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C.LWSP {//
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encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
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args_disass: "{name(rd)}, sp, {uimm:#05x}";
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val offs[XLEN] <= X[2] + uimm;
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X[rd] <= sext(MEM[offs]{32});
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}
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// order matters as C.JR is a special case of C.MV
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C.MV {//(RV32)
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encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
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args_disass: "{name(rd)}, {name(rs2)}";
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X[rd] <= X[rs2];
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}
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C.JR(no_cont) {//(RV32)
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encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
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args_disass: "{name(rs1)}";
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PC <= X[rs1];
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}
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// order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD
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C.ADD {//(RV32)
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encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
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args_disass: "{name(rd)}, {name(rs2)}";
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X[rd] <= X[rd] + X[rs2];
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}
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C.JALR(no_cont) {//(RV32)
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encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
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args_disass: "{name(rs1)}";
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X[1] <= PC+2;
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PC<=X[rs1];
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}
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C.EBREAK(no_cont) {//(RV32)
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encoding:b100 | b1 | b00000 | b00000 | b10;
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raise(0, 3);
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}
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C.SWSP {//
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encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
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args_disass: "{name(rs2)}, {uimm:#05x}(sp)";
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val offs[XLEN] <= X[2] + uimm;
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MEM[offs]{32} <= X[rs2];
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}
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DII {
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encoding:b000 | b0 | b00000 | b00000 | b00;
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raise(0, 2);
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}
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}
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}
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InsructionSet RV32FC extends RV32IC{
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constants {
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FLEN
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}
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registers {
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[31:0] F[FLEN]
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}
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instructions{
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C.FLW {
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encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
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args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd+8] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd+8] <= (upper<<32) | zext(res, FLEN);
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}
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}
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C.FSW {
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encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
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args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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MEM[offs]{32}<=F[rs2+8]{32};
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}
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C.FLWSP {
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encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
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args_disass:"f{rd}, {uimm}(x2)";
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val offs[XLEN] <= X[2]+uimm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<32) | zext(res, FLEN);
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}
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}
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C.FSWSP {
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encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
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args_disass:"f{rs2}, {uimm}(x2), ";
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val offs[XLEN] <= X[2]+uimm;
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MEM[offs]{32}<=F[rs2]{32};
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}
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}
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}
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InsructionSet RV32DC extends RV32IC{
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constants {
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FLEN
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}
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registers {
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[31:0] F[FLEN]
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}
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instructions{
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C.FLD { //(RV32/64)
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encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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val res[64] <= MEM[offs]{64};
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if(FLEN==64)
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F[rd+8] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd+8] <= (upper<<64) | res;
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}
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}
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C.FSD { //(RV32/64)
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encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8]+uimm;
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MEM[offs]{64}<=F[rs2+8]{64};
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}
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C.FLDSP {//(RV32/64)
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encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
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args_disass:"f{rd}, {uimm}(x2)";
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val offs[XLEN] <= X[2]+uimm;
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val res[64] <= MEM[offs]{64};
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | zext(res, FLEN);
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}
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}
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C.FSDSP {//(RV32/64)
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encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
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args_disass:"f{rs2}, {uimm}(x2), ";
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val offs[XLEN] <= X[2]+uimm;
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MEM[offs]{64}<=F[rs2]{64};
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}
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}
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}
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InsructionSet RV64IC extends RV32IC {
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instructions{
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C.LD {//(RV64/128)
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encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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args_disass: "{name(8+rd)}, {uimm},({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8] + uimm;
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X[rd+8]<=sext(MEM[offs]{64});
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}
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C.SD { //(RV64/128)
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encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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args_disass: "{name(8+rs2)}, {uimm},({name(8+rs1)})";
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val offs[XLEN] <= X[rs1+8] + uimm;
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MEM[offs]{64} <= X[rs2+8];
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}
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C.SUBW {//(RV64/128, RV32 res)
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encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";
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val res[32] <= X[rd+8]{32} - X[rs2+8]{32};
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X[rd+8] <= sext(res);
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}
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C.ADDW {//(RV64/128 RV32 res)
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encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
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args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";
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val res[32] <= X[rd+8]{32} + X[rs2+8]{32};
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X[rd+8] <= sext(res);
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}
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C.ADDIW {//(RV64/128)
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encoding:b001 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
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args_disass: "{name(rs1)}, {imm:#05x}";
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if(rs1 != 0){
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val res[32] <= X[rs1]{32}'s + imm;
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X[rs1] <= sext(res);
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}
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}
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C.SRLI {//(RV64)
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encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shrl(X[rs1_idx], shamt);
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}
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C.SRAI {//(RV64)
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encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shra(X[rs1_idx], shamt);
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}
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C.SLLI {//(RV64)
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encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
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args_disass: "{name(rs1)}, {shamt}";
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if(rs1 == 0) raise(0, 2);
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X[rs1] <= shll(X[rs1], shamt);
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}
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C.LDSP {//(RV64/128
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encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
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args_disass:"{name(rd)}, {uimm}(sp)";
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val offs[XLEN] <= X[2] + uimm;
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if(rd!=0) X[rd]<=sext(MEM[offs]{64});
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}
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C.SDSP {//(RV64/128)
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encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
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args_disass:"{name(rs2)}, {uimm}(sp)";
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val offs[XLEN] <= X[2] + uimm;
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MEM[offs]{64} <= X[rs2];
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}
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}
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}
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InsructionSet RV128IC extends RV64IC {
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instructions{
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C.SRLI {//(RV128)
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encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shrl(X[rs1_idx], shamt);
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}
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C.SRAI {//(RV128)
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encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "{name(8+rs1)}, {shamt}";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shra(X[rs1_idx], shamt);
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}
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C.SLLI {//(RV128)
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encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
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args_disass: "{name(rs1)}, {shamt}";
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if(rs1 == 0) raise(0, 2);
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X[rs1] <= shll(X[rs1], shamt);
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}
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C.LQ { //(RV128)
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encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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}
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C.SQ { //(RV128)
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encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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}
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C.SQSP {//(RV128)
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encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
|
|
}
|
|
}
|
|
}
|