248 lines
8.7 KiB
C++
248 lines
8.7 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "sysc/SiFive/gpio.h"
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#include "sysc/sc_comm_singleton.h"
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#include "scc/report.h"
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#include "scc/utilities.h"
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#include "sysc/SiFive/gen/gpio_regs.h"
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namespace sysc {
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gpio::gpio(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMED(pins_o, 32)
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, NAMED(pins_i, 32)
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, NAMED(iof0_o, 32)
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, NAMED(iof1_o, 32)
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, NAMED(iof0_i, 32)
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, NAMED(iof1_i, 32)
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, NAMEDD(gpio_regs, regs)
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, NAMED(write_to_ws, false){
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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auto pins_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp,
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tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
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this->pin_input(tag, gp, delay);
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return tlm::TLM_COMPLETED;
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};
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auto i=0U;
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for(auto& s:pins_i){
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s.register_nb_transport(pins_i_cb, i);
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++i;
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}
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auto iof0_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<bool>& gp,
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tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
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last_iof0[tag]=gp.get_value();
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this->iof_input(tag, 0, gp, delay);
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return tlm::TLM_COMPLETED;
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};
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i=0;
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for(auto& s:iof0_i){
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s.register_nb_transport(iof0_i_cb, i);
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++i;
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}
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auto iof1_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<bool>& gp,
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tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
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last_iof1[tag]=gp.get_value();
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this->iof_input(tag, 1, gp, delay);
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return tlm::TLM_COMPLETED;
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};
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i=0;
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for(auto& s:iof1_i){
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s.register_nb_transport(iof1_i_cb, i);
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++i;
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}
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regs->port.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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if (!this->regs->in_reset()) {
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reg.put(data);
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// read r_ports and update pins_io
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update_pins();
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}
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return true;
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});
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regs->iof_en.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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if (!this->regs->in_reset()) {
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enable_outputs(data, regs->r_iof_sel);
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reg.put(data);
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}
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return true;
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});
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regs->iof_sel.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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if (!this->regs->in_reset()) {
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enable_outputs(regs->r_iof_en, data);
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reg.put(data);
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}
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return true;
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});
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}
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gpio::~gpio() {}
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void gpio::before_end_of_elaboration() {
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if(write_to_ws.get_value()) {
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LOG(TRACE)<<"Adding WS handler for "<<(std::string{"/ws/"}+name());
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handler=std::make_shared<WsHandler>();
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sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"}+name()).c_str(), handler);
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}
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}
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void gpio::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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void gpio::clock_cb() {
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this->clk = clk_i.read();
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}
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tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, size_t i, sc_dt::sc_logic val) {
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sc_core::sc_time delay{SC_ZERO_TIME};
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tlm::tlm_phase phase{ tlm::BEGIN_REQ };
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_response_status(tlm::TLM_OK_RESPONSE);
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gp.set_value(val);
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pins_o.at(i)->nb_transport_fw(gp, phase, delay);
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return phase;
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}
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void gpio::update_pins() {
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sc_core::sc_inout_rv<32>::data_type out_val;
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tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
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for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
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if((regs->iof_en&mask == 0) || (iof0_i[i].size()==0 && iof1_i[i].size()==0)){
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auto val = regs->r_output_en&mask?
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regs->r_port&mask?
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sc_dt::Log_1:
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sc_dt::Log_0:
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sc_dt::Log_Z;
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tlm::tlm_phase phase = write_output(gp, i, val);
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}
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}
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}
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void gpio::enable_outputs(uint32_t new_iof_en, uint32_t new_iof_sel) {
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auto changed_bits = (regs->r_iof_en^new_iof_en) | (regs->r_iof_sel^new_iof_sel);
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tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
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for(size_t i=0, mask=1; i<32; ++i, mask<<=1){
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if(changed_bits&mask){
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if(new_iof_en&mask){
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if((regs->r_iof_sel&mask)==0 && iof0_i[i].size()>0){
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tlm::tlm_phase phase = write_output(gp, i, last_iof0[i]?sc_dt::Log_1:sc_dt::Log_0);
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} else if((regs->r_iof_sel&mask)==1 && iof1_i[i].size()>0)
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tlm::tlm_phase phase = write_output(gp, i, last_iof1[i]?sc_dt::Log_1:sc_dt::Log_0);
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} else {
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auto val = regs->r_output_en&mask?
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regs->r_port&mask?sc_dt::Log_1:sc_dt::Log_0:
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sc_dt::Log_Z;
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tlm::tlm_phase phase = write_output(gp, i, val);
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}
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}
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}
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}
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void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp, sc_core::sc_time& delay) {
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if(delay>SC_ZERO_TIME){
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wait(delay);
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delay=SC_ZERO_TIME;
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}
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switch(gp.get_value().value()){
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case sc_dt::Log_1:
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regs->r_value|=1<<tag;
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forward_pin_input(tag, gp);
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break;
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case sc_dt::Log_0:
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regs->r_value&=~(1<<tag);
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forward_pin_input(tag, gp);
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break;
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}
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}
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void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp) {
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const auto mask = 1U<<tag;
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if(regs->iof_en&mask){
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auto& socket = regs->iof_sel&mask?iof1_o[tag]:iof0_o[tag];
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tlm::tlm_signal_gp<> new_gp;
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for(size_t i=0; i<socket.size(); ++i){
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sc_core::sc_time delay{SC_ZERO_TIME};
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tlm::tlm_phase phase{tlm::BEGIN_REQ};
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new_gp.set_command(tlm::TLM_WRITE_COMMAND);
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new_gp.set_response_status(tlm::TLM_OK_RESPONSE);
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new_gp.set_value(gp.get_value().value()==sc_dt::Log_1);
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new_gp.update_extensions_from(gp);
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socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
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}
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}
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}
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void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay) {
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if(delay>SC_ZERO_TIME){
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wait(delay);
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delay=SC_ZERO_TIME;
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}
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const auto mask = 1U<<tag;
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if(regs->r_iof_en&mask){
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const auto idx = regs->r_iof_sel&mask?1:0;
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if(iof_idx == idx){
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auto& socket = pins_o[tag];
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for(size_t i=0; i<socket.size(); ++i){
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sc_core::sc_time delay{SC_ZERO_TIME};
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tlm::tlm_phase phase{tlm::BEGIN_REQ};
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tlm::tlm_signal_gp<sc_logic> new_gp;
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new_gp.set_command(tlm::TLM_WRITE_COMMAND);
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auto val = gp.get_value();
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new_gp.set_value(val?sc_dt::Log_1:sc_dt::Log_0);
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new_gp.copy_extensions_from(gp);
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socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
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gp.update_extensions_from(new_gp);
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}
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}
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}
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}
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} /* namespace sysc */
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