66 lines
1.9 KiB
C++
66 lines
1.9 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright 2017 eyck@minres.com
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations under
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// the License.
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////////////////////////////////////////////////////////////////////////////////
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#include "sysc/SiFive/uart.h"
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#include "scc/report.h"
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#include "scc/utilities.h"
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#include "sysc/SiFive/gen/uart_regs.h"
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namespace sysc {
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uart::uart(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMEDD(uart_regs, regs) {
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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if (!this->regs->in_reset()) {
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reg.put(data);
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this->transmit_data();
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}
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return true;
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});
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}
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uart::~uart() {}
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void uart::clock_cb() { this->clk = clk_i.read(); }
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void uart::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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void uart::transmit_data() {
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if(regs->r_txdata.data != '\r') queue.push_back(regs->r_txdata.data);
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if (queue.size() >> 0 && (regs->r_txdata.data == '\n' || regs->r_txdata.data == 0)) {
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LOG(INFO) << this->name() << " transmit: '" << std::string(queue.begin(), queue.end()) << "'";
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queue.clear();
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}
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}
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} /* namespace sysc */
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